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11. 发明专利

JP2009140322A Timing control circuit and semiconductor memory device 审中-公开
标题翻译：时序控制电路和半导体存储器件
公开(公告)号：JP2009140322A
公开(公告)日：2009-06-25
申请号：JP2007317161
申请日：2007-12-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TAKAI YASUHIRO , KOTABE AKIRA , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU
IPC分类号： G06F1/06 , H03K5/00
CPC分类号： G11C11/4076 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C19/00 , H03K5/131 , H03K5/14 , H03K2005/00058 , H03K2005/00241
摘要： PROBLEM TO BE SOLVED: To reduce the rate at which the amount of delay in a timing signal changes as a process or a working environment or the like changes.
SOLUTION: A timing control circuit has a timing control circuit DLY 1 which receives the input of a clock signal CKa with a period T1 and an activation signal ACT and which then generates a fine-tuning timing signal FT such that the amount of delay from a clock is td=m*T1+tda where (m) is a positive or negative integer and tda is the amount of delay caused by an analog delaying element. The timing control circuit DLY 1 comprises a coarse-tuning delay circuit CD and a fine-tuning delay circuit FD. The coarse-tuning delay circuit CD has a counter for counting the rising edges of the clock signals CKa after receiving the activation signal ACT, and outputs a coarse-tuning timing signal CT such that the amount of delay from the rise of the clock signal CKa is m*T1. The fine-tuning delay circuit FD has a plurality of analog delaying elements and outputs a fine-tuning timing signal FT such that the amount of delay from the coarse-tuning timing signal CT is tda.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了降低定时信号的延迟量随着过程或工作环境等而改变的速率的变化。定时控制电路具有定时控制电路DLY 1，其接收时钟信号CKa的输入，周期T1和激活信号ACT，然后产生微调定时信号FT，从时钟的延迟是td = m * T1 + tda其中（m）是正或负整数，tda是由模拟延迟元件引起的延迟量。定时控制电路DLY1包括粗调延迟电路CD和微调延迟电路FD。粗调延迟电路CD具有用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并且输出粗调定时信号CT，使得从时钟信号CKa的上升起的延迟量是m * T1。微调延迟电路FD具有多个模拟延迟元件，并输出微调定时信号FT，使得来自粗调定时信号CT的延迟量为tda。版权所有（C）2009，JPO＆INPIT

12. 发明专利

JP2009071594A Timing control circuit, and semiconductor memory 有权
标题翻译：时序控制电路和半导体存储器
公开(公告)号：JP2009071594A
公开(公告)日：2009-04-02
申请号：JP2007238013
申请日：2007-09-13
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TAKAI YASUHIRO , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , NAKATANI HIROAKI
IPC分类号： H03K5/00 , G06F1/06 , G11C11/407 , G11C11/4076 , H03K5/13 , H03L7/081
CPC分类号： H03K5/135 , G11C7/04 , G11C7/1072 , G11C7/222 , G11C11/4076 , G11C19/00
摘要： PROBLEM TO BE SOLVED: To provide a timing control circuit capable of reducing access time by generating timing with small delay variation with respect to change in a process, operation environment, or the like, and to provide a semiconductor memory equipped with the timing control circuit. SOLUTION: A first clock signal having a frequency T1, and a second clock group (CKb) of a frequency T2 are input in the timing control circuit. The timing control circuit is equipped with a coarse adjustment delay circuit (CD) and a fine adjustment delay circuit (FD). The coarse adjustment delay circuit (CD) includes a counter for counting a rise time edge of the first clock signal by activation of an activation signal, and generates a coarse adjustment timing signal (CT) whose delay amount from the first clock signal substantially equals to m×T1. The fine adjustment delay circuit (FD) consists of L pieces of parallel multi-phase clock control delay circuits, and delays sampling timing of the coarse adjustment timing signal (CT) of the second clock group of L phases, respectively, by n×(T2/L), and makes the signal a fine adjustment timing signal (FT) by OR of the delayed pulses. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种定时控制电路，其能够通过相对于处理，操作环境等的变化产生具有小的延迟变化的定时来减少访问时间，并且提供配备有定时控制电路。解决方案：具有频率T1的第一时钟信号和频率T2的第二时钟组（CKb）被输入到定时控制电路中。定时控制电路配备有粗调延迟电路（CD）和微调延迟电路（FD）。粗调延迟电路（CD）包括用于通过激活激活信号对第一时钟信号的上升时间边缘进行计数的计数器，并且生成其第一时钟信号的延迟量基本上等于 m×T1。微调延迟电路（FD）由L个并行多相时钟控制延迟电路构成，分别延迟L相的第二时钟组的粗调定时信号（CT）的采样定时n×（ T2 / L），通过延迟脉冲的或使信号成为微调定时信号（FT）。版权所有（C）2009，JPO＆INPIT

13. 发明专利

JP2008171476A Semiconductor memory device, and its sense amplifier circuit 有权
标题翻译：半导体存储器件及其感测放大器电路
公开(公告)号：JP2008171476A
公开(公告)日：2008-07-24
申请号：JP2007001455
申请日：2007-01-09
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： AKIYAMA SATORU , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , NAKATANI HIROAKI , MIYATAKE SHINICHI , WATANABE YUKO
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device achieving high integration, low power consumption and high speed operation. SOLUTION: The semiconductor memory device has a sense amplifier composed of a plurality of pull-down circuits and one pull-up circuit. Also, a transistor constituting a pull-down circuit among a plurality of pull-down circuits is larger than a transistor constituting the other pull-down circuit in constant such as channel length and channel width. Further, the pull-down circuit having larger constant of the transistor is activated first, after that, the other pull-down circuit and the pull-up circuit are activated for read-out. Further, a data line and the pull-down circuit driven first are connected by a NMOS transistor, and activation of the pull-down circuit is controlled by activating or inactivating the NMOS transistor. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供实现高集成度，低功耗和高速操作的半导体存储器件。解决方案：半导体存储器件具有由多个下拉电路和一个上拉电路组成的读出放大器。此外，构成多个下拉电路中的下拉电路的晶体管的尺寸大于构成另一个下拉电路的晶体管，其通道长度和沟道宽度是恒定的。此外，具有较大的晶体管常数的下拉电路首先被激活，之后，另一个下拉电路和上拉电路被激活用于读出。此外，首先通过NMOS晶体管连接驱动的数据线和下拉电路，并且通过激活或去激活NMOS晶体管来控制下拉电路的激活。版权所有（C）2008，JPO＆INPIT

14. 发明专利

JP2005340356A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2005340356A
公开(公告)日：2005-12-08
申请号：JP2004154753
申请日：2004-05-25
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKEMURA RIICHIRO , AKIYAMA SATORU , HANZAWA SATORU , SEKIGUCHI TOMONORI , KAJITANI KAZUHIKO
IPC分类号： H01L27/108 , G11C11/24 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of realizing high speed operation, and to provide a semiconductor storage device capable of realizing high integration and high speed operation. SOLUTION: Transistors MT1, MT2 are disposed on opposite sides of a diffusion layer region DIFF (SN) to which a capacitor CAP for storing information is connected, and other diffusion layer regions DIFF of the respective transistors MT1, MT2 are connected to the same bit line BL. When access is made to the memory cell MC, the two transistors MT1, MT2 are activated and read. Further, when write operation is made for the memory cell MC, electric charges are written into the capacitor using the two transistors MT1, MT2. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供能够实现高速运行的半导体存储装置，并提供能够实现高集成度和高速运行的半导体存储装置。解决方案：晶体管MT1，MT2设置在扩散层区域DIFF（SN）的相对侧，扩散层区域DIFF（SN）连接有用于存储信息的电容器CAP，并且各个晶体管MT1，MT2的其它扩散层区域DIFF连接到相同的位线BL。当访问存储单元MC时，两个晶体管MT1，MT2被激活并被读取。此外，当对存储单元MC进行写入操作时，使用两个晶体管MT1，MT2将电荷写入电容器。版权所有（C）2006，JPO＆NCIPI

15. 发明专利

JP2006186150A MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR DESIGN APPARATUS 审中-公开
公开(公告)号：JP2006186150A
公开(公告)日：2006-07-13
申请号：JP2004379071
申请日：2004-12-28
申请人： HITACHI LTD , ELPIDA MEMORY INC
发明人： AKIYAMA SATORU , SEKIGUCHI TOMONORI , KAWAHARA TAKAYUKI , KAJITANI KAZUHIKO
IPC分类号： H01L21/82 , G06F17/50 , H01L21/00 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor storage device and a semiconductor design apparatus capable of realizing ease of design or reduction in a design period. SOLUTION: In the case of verifying a designed memory array for example, the manufacturing method uses a read signal quantity VS_EFF of a memory cell formalized by functions of various parameters VN(ΔVBDL), VN(ΔVTN), VN(IJ) including various distributions, calculates the value of the read signal quantity VS_EFF by using values extracted at random from the distribution of each of the various parameters, discriminates the propriety of the memory cell on the basis of a result of the calculation, and applies the calculation of the value of the read signal quantity VS_EFF and the discrimination of the propriety of the memory cell to many memory cells provided with the memory array. Consequently, a total number of defective bits or the like obtained by the above process is used for an evaluation criterion of the memory array. COPYRIGHT: (C)2006,JPO&NCIPI

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