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1. 发明专利

JP2008186547A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008186547A
公开(公告)日：2008-08-14
申请号：JP2007020986
申请日：2007-01-31
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKATANI HIROAKI , TAKEMURA RIICHIRO , AKIYAMA SATORU , SEKIGUCHI TOMONORI , NAKAMURA MASAYUKI , MIYATAKE SHINICHI
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide technology to control a shared MOS transistor gate voltage that can improve the sensing speed and quickly read data by preventing data inversion due to noise and reducing the bit line capacity when used for the low voltage. SOLUTION: The sensing speed is increased via a gate voltage control circuit of the shared MOS transistor connecting a sense amplifier and a memory cell array by considering the noise at sensing, lowering the shared MOS transistor gate voltage (SHR) in two steps and reducing the amplified bit line capacity. Thus, the column selection signal is quickly started, and the data read time is shortened. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供技术来控制共享的MOS晶体管栅极电压，其可以通过防止由于噪声导致的数据反转并且当用于低电压时降低位线容量来提高感测速度并快速读取数据。解决方案：通过考虑传感噪声连接读出放大器和存储单元阵列的共享MOS晶体管的栅极电压控制电路提高感测速度，分两步降低共享MOS晶体管栅极电压（SHR）并降低放大的位线容量。因此，列选择信号快速启动，数据读取时间缩短。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2008028055A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008028055A
公开(公告)日：2008-02-07
申请号：JP2006197602
申请日：2006-07-20
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： AKIYAMA SATORU , TSUCHIYA RYUTA , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , NAKAMURA MASAYUKI , YAMAZAKI YASUSHI , SHIRATAKE SHIGERU
IPC分类号： H01L21/8242 , H01L21/3205 , H01L23/52 , H01L27/108
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability. SOLUTION: The gate electrode 7 of the memory cell transistor of the DRAM is formed of an n-type polycrystalline silicon film 7n and a W film 8 laminated thereon. Part of the polycrystalline silicon film 7n is embedded within the groove 13 formed in the silicon substrate 1 to increase the effective channel length of the memory cell transistor. The other part of the polycrystalline silicon film 7n is projected above the groove 13 and the top face thereof is located above the surface of the silicon substrate 1 (p-type well 3), so that the distances are ensured between the W film 8 and the source, and between the W film 8 and the drain (n-type semiconductor regions 9a, 9b). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现降低功耗，高速运行和高可靠性的DRAM。解决方案：DRAM的存储单元晶体管的栅极7由层叠在其上的n型多晶硅膜7n和W膜8形成。多晶硅膜7n的一部分嵌入到形成在硅衬底1中的槽13内，以增加存储单元晶体管的有效沟道长度。多晶硅膜7n的另一部分突出在槽13的上方，其顶面位于硅衬底1（p型阱3）的表面上方，从而确保W膜8与源极，以及W膜8和漏极（n型半导体区域9a，9b）之间。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007179681A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007179681A
公开(公告)日：2007-07-12
申请号：JP2005378490
申请日：2005-12-28
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： HANZAWA SATORU , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C11/4096 , G11C11/407
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a semiconductor memory such as a DRAM, and achieves the expansion of an operation margin or reduction of power consumption. SOLUTION: Such a columnar circuit is provided for instance that a signal read out to a local input/output line LIO from a sense amplifier array SAA is amplified by sub-amplifiers and transferred to a main input/output line MIO. On each sub-amplifier, a current control circuit IC is prepared of which currents of two kinds can be set in accordance with e.g. read starting signals RD1, 2. The RD1, 2 are formed at timing corresponded to the number of cycles of burst read-out operation by the control of a timing control circuit. The current of the current control circuit IC is set to be large by the RD1 in the burst read-out operation cycle of a time immediately after the activation of a bank, and the current of the current control circuit IC is set to be small by the RD2 in the succeeding read-out operation. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括诸如DRAM的半导体存储器的半导体器件，并且实现了操作裕度的扩大或功耗的降低。解决方案：提供这种柱状电路，例如从读出放大器阵列SAA读出到本地输入/输出线LIO的信号由子放大器放大并被传送到主输入/输出线MIO。在每个子放大器上，准备电流控制电路IC，其中根据例如可以设置两种电流。读取起始信号RD1,2。RD1,2在与定时控制电路的控制的脉冲串读出操作的周期数相对应的定时形成。电流控制电路IC的电流通过在激活组之后的时间的脉冲串读出操作周期中的RD1被设置为较大，并且电流控制电路IC的电流被设置为小 RD2在后续的读出操作中。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2007042176A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2007042176A
公开(公告)日：2007-02-15
申请号：JP2005223012
申请日：2005-08-01
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , HANZAWA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C29/42 , G11C11/401 , G11C29/04
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a wide operating margin at the operation to make it finer, while suppressing an area penalty.
SOLUTION: An error code correcting system consisting of 64 bits data bit and 9 bits check bit with respect to a memory array ARY such as a DRAM is introduced, for instance, and an error correction code circuit ECC according to the above arrangement is disposed adjacent to a sense amplifier column SAA. In addition to a regular memory array consisting of such memory array ARY, a redundant memory array similarly furnished with the SAA and the adjacent ECC is provided in a chip to relieve a defect developed at the manufacture. In the ECC, error is corrected at an activate command, and the check bit is stored at a precharge command.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其在操作时具有较宽的操作裕度，以使其更细，同时抑制区域损失。解决方案：例如，引入了相对于诸如DRAM的存储器阵列ARY由64位数据位和9位校验位组成的错误代码校正系统，以及根据上述布置的纠错码电路ECC 被布置在与感测放大器列SAA相邻的位置。除了由这种存储器阵列ARY组成的常规存储器阵列之外，在芯片中提供类似于SAA和相邻ECC的冗余存储器阵列，以减轻在制造过程中产生的缺陷。在ECC中，在激活命令下修正错误，校验位存储在预充电命令中。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2006277870A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006277870A
公开(公告)日：2006-10-12
申请号：JP2005098027
申请日：2005-03-30
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , OSAKA HIDEKI , IDO TATSUMI , NAGASHIMA YASUSHI , KATAGIRI MITSUAKI , ANJO ICHIRO
IPC分类号： G11C11/401
CPC分类号： G11C8/12 , G11C5/02 , G11C5/04 , G11C11/4074 , G11C11/4096 , H01L24/50
摘要： PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of a command/address external terminal group and a data input/output terminal group to the level of a 1-chip article, in a semiconductor storage device provided with a plurality of laminated memory chips. SOLUTION: The semiconductor storage device comprises a base board 101 provided with the command/address external terminal group CA, the data input/output external terminal group DQ and a single-chip selection external terminal CS, and the plurality of memory chips 110-113 laminated on the base board 101 and capable of reading operation and writing operation independently, respectively. The terminals CA, DQ and CS are all connected to an interface chip 120. The interface chip 120 is provided with a chip selection signal generating circuit, capable of individually activating the plurality of memory chips 110-113, on the basis of address signals supplied via the terminal CA and chip selection signals supplied via the terminal CS. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了将命令/地址外部端子组和数据输入/输出端子组的寄生电容减小到1芯片制品的水平，在设置有多个层叠的半导体存储装置中内存芯片解决方案：半导体存储装置包括设置有命令/地址外部端子组CA，数据输入/输出外部端子组DQ和单片选择外部端子CS的基板101，以及多个存储器芯片 110-113分别层叠在基板101上，并且能够分别独立地读取操作和写入操作。端子CA，DQ和CS都连接到接口芯片120.接口芯片120设有芯片选择信号发生电路，其能够基于提供的地址信号单独激活多个存储器芯片110-113 经由终端CA和经由终端CS提供的芯片选择信号。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006172683A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006172683A
公开(公告)日：2006-06-29
申请号：JP2005172077
申请日：2005-06-13
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , AKIYAMA SATORU , TAKEMURA RIICHIRO , HANZAWA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C11/404 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device especially useful for miniaturizing DRAM. SOLUTION: A write command is input from the outside, the voltages of bit lines BLT and BLB are constituted of VDL and VSS, voltages are written in the storage node SN of a capacitor via a memory cell transistor according to the threshold values (LVT: low threshold voltage, MVT: middle threshold voltage, and HVT: high threshold voltage) of the memory cell transistor. Then, a plate line PL connected to the plate side of the capacitor is driven from a voltage VPL to a voltage VPH. When the voltage of the storage node SN is increased by coupling, the bit line BLT is reduced from the voltage VDL to the voltage VDP, the voltages excessively written in the storage SN are reduced according to the sizes of the threshold voltages of the memory cell transistor, and a variance in voltages of the storage node SN caused by the variance of the threshold voltages is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供对DRAM的小型化特别有用的半导体存储装置。解决方案：从外部输入写入命令，位线BLT和BLB的电压由VDL和VSS构成，电压根据阈值经由存储单元晶体管写入电容器的存储节点SN中（LVT：低阈值电压，MVT：中间阈值电压以及HVT：高阈值电压）。然后，将连接到电容器的板侧的板线PL从电压VPL驱动到电压VPH。当存储节点SN的电压通过耦合增加时，位线BLT从电压VDL减小到电压VDP，过度写入存储SN的电压根据存储单元的阈值电压的大小而减小晶体管，并且由阈值电压的变化引起的存储节点SN的电压变化减小。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2004171742A Semiconductor device 审中-公开
公开(公告)号：JP2004171742A
公开(公告)日：2004-06-17
申请号：JP2003373026
申请日：2003-10-31
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , SAKATA TAKESHI , MIYATAKE SHINICHI , NODA HIROMASA , KAJITANI KAZUHIKO
IPC分类号： H01L21/8242 , G11C7/00 , G11C11/4076 , G11C11/409 , G11C11/4096 , H01L27/02 , H01L27/108 , H01L31/109
CPC分类号： G11C11/4096 , G11C11/4076 , G11C2207/002 , H01L27/0207 , H01L27/10882 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To realize both high-speed writing and stable rewriting in the DRAM of a high-speed cycle. SOLUTION: A word line and a Y selection line YS1 are simultaneously activated, write data is written from an IO line IOt/b in a selection data line DL1t/b, and the data of a memory cell is read at an adjacent nonselection amplifier. By dividing the source node of the cross couple CC of a sense amplifier connected to each data line pair for each Y selection line, the driving of the source node by a write selection cross coupling is prevented. The write data is written during reading, a high-speed writing operation is realized, and the driving of the source node by the write sense amplifier is prevented. Thus, at the adjacent sense amplifier, a stable reading operation is realized without being influenced by the write sense amplifier. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2009158514A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2009158514A
公开(公告)日：2009-07-16
申请号：JP2007331571
申请日：2007-12-25
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： YAMADA YASUTOSHI , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , KAJITANI KAZUHIKO
IPC分类号： H01L21/8242 , G11C11/401 , H01L27/108
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C8/04 , G11C8/08 , G11C8/12 , G11C11/4094 , G11C11/4097
摘要： PROBLEM TO BE SOLVED: To overcome the problems that when a DRAM is subject to micro-fabrication and a vertical MOS transistor is used as a memory cell, parasitic capacitance increases among adjoining word lines, and it becomes necessary to reduce coupling noise arising because of the parasitic capacitance, or it also becomes necessary to suppress an increase in chip size when reducing coupling noise among the word lines. SOLUTION: A twist connection part WCA 1 for changing wiring order of word lines (upper-layer word line UWL) is provided at a substantially central section of word lines, and a level stabilizing circuit TR is arranged in the lower area of the twist connection part WCA 1 to output potential level of the word line under a non-selection state. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了克服当DRAM受到微制造而使用垂直MOS晶体管作为存储单元的问题时，相邻字线之间的寄生电容增加，并且需要减少耦合噪声由于寄生电容而产生，或者当减少字线之间的耦合噪声时，还需要抑制芯片尺寸的增加。解决方案：用于改变字线布线顺序的扭转连接部分WCA1（上层字线UWL）设置在字线的大致中央部分，电平稳定电路TR布置在扭转连接部WCA1，以在非选择状态下输出字线的电位。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2010009667A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2010009667A
公开(公告)日：2010-01-14
申请号：JP2008167059
申请日：2008-06-26
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： KAJITANI KAZUHIKO , YOSHIDA SOICHIRO , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , YAMADA YASUTOSHI
IPC分类号： G11C11/404 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can reduce a voltage noise caused at a potential of a plate which is a counter electrode of an information storage capacitor when data is read from a memory cell to a bit line or when data is written or re-written in the memory cell.
SOLUTION: The semiconductor memory device has a memory cell array where a plurality of memory cells are arranged in an array form, a word line driver, a sense amplifier, and a plurality of first dummy capacitors which are arranged in a boundary area of the memory cell array and the word line driver and/or in a boundary area of the memory cell array and the sense amplifier, wherein one side of electrodes of the first dummy capacitors is commonly connected and a first potential is applied, and the other side of the information storage capacitors of the respective memory cells and the other side of the electrodes of the first dummy capacitors are commonly connected and a second potential is applied.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种半导体存储器件，其能够降低在将数据从存储单元读取到位线时作为信息存储电容器的对电极的电位的电位引起的电压噪声，或者当数据被写入或重写在存储单元中时。解决方案：半导体存储器件具有存储单元阵列，其中多个存储单元以阵列形式布置，字线驱动器，读出放大器和多个第一虚拟电容器，其布置在边界区域中存储单元阵列和字线驱动器和/或在存储单元阵列和读出放大器的边界区域中，其中第一虚拟电容器的电极的一侧共同连接并且施加第一电位，而另一个各个存储单元的信息存储电容器的侧面和第一虚拟电容器的电极的另一侧共同连接，并施加第二电位。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2008171476A Semiconductor memory device, and its sense amplifier circuit 有权
标题翻译：半导体存储器件及其感测放大器电路
公开(公告)号：JP2008171476A
公开(公告)日：2008-07-24
申请号：JP2007001455
申请日：2007-01-09
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： AKIYAMA SATORU , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , NAKATANI HIROAKI , MIYATAKE SHINICHI , WATANABE YUKO
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , H01L27/10897
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device achieving high integration, low power consumption and high speed operation. SOLUTION: The semiconductor memory device has a sense amplifier composed of a plurality of pull-down circuits and one pull-up circuit. Also, a transistor constituting a pull-down circuit among a plurality of pull-down circuits is larger than a transistor constituting the other pull-down circuit in constant such as channel length and channel width. Further, the pull-down circuit having larger constant of the transistor is activated first, after that, the other pull-down circuit and the pull-up circuit are activated for read-out. Further, a data line and the pull-down circuit driven first are connected by a NMOS transistor, and activation of the pull-down circuit is controlled by activating or inactivating the NMOS transistor. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供实现高集成度，低功耗和高速操作的半导体存储器件。解决方案：半导体存储器件具有由多个下拉电路和一个上拉电路组成的读出放大器。此外，构成多个下拉电路中的下拉电路的晶体管的尺寸大于构成另一个下拉电路的晶体管，其通道长度和沟道宽度是恒定的。此外，具有较大的晶体管常数的下拉电路首先被激活，之后，另一个下拉电路和上拉电路被激活用于读出。此外，首先通过NMOS晶体管连接驱动的数据线和下拉电路，并且通过激活或去激活NMOS晶体管来控制下拉电路的激活。版权所有（C）2008，JPO＆INPIT

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