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121. 发明专利

JP2009102190A Silicon manufacturing apparatus 审中-公开
标题翻译：硅制造设备
公开(公告)号：JP2009102190A
公开(公告)日：2009-05-14
申请号：JP2007274831
申请日：2007-10-23
申请人： Covalent Materials Corp , Kinotech Solar Energy Corp , コバレントマテリアル株式会社 , 株式会社キノテック・ソーラーエナジー
发明人： OHASHI TADASHI , MATSUMURA TAKASHI , TAKEUCHI YOSHINORI , SAKAKI DAISUKE
IPC分类号： C01B33/033
摘要： PROBLEM TO BE SOLVED: To provide a silicon manufacturing apparatus capable of simplifying the whole apparatus and manufacturing silicon at a low cost. SOLUTION: The silicon manufacturing apparatus includes a reaction tube 10, a heating furnace 20 for heating the reaction tube 10, a zinc supply pipe 30 for supplying zinc to the reaction tube 10, a zinc charging part 40 for charging zinc into the zinc supply pipe 30, and a silicon compound supply pipe 50 for supplying a silicon compound into the reaction tube 10, wherein a connection part 30b of the zinc supply pipe 30 and a heating part 30a are provided in a heating region (α) of the heating furnace 20. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供能够以低成本简化整个装置并制造硅的硅制造装置。解决方案：硅制造装置包括反应管10，用于加热反应管10的加热炉20，用于向反应管10供给锌的锌供给管30，将锌充入到锌的充电部40 锌供给管30和用于将硅化合物供给到反应管10中的硅化合物供给管50，其中锌供给管30的连接部30b和加热部30a设置在加热区域（α）加热炉20.版权所有（C）2009，JPO＆INPIT

122. 发明专利

JP4259881B2 Cleaning method of a silicon wafer 有权
公开(公告)号：JP4259881B2
公开(公告)日：2009-04-30
申请号：JP2003001131
申请日：2003-01-07
申请人：コバレントマテリアル株式会社
发明人：宏治泉妻 , 浩司荒木 , 一日児鹿島
IPC分类号： H01L21/304

123. 发明专利

JP2009094229A Field-effect transistor and production process therefor 有权
标题翻译：场效应晶体管及其生产工艺
公开(公告)号：JP2009094229A
公开(公告)日：2009-04-30
申请号：JP2007262344
申请日：2007-10-05
申请人： Covalent Materials Corp , Toshiba Corp , コバレントマテリアル株式会社 , 株式会社東芝
发明人： TEZUKA TSUTOMU , TOYODA EIJI
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/78
CPC分类号： H01L29/7842 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66795 , H01L29/66818 , H01L29/785 , H01L29/78696
摘要： PROBLEM TO BE SOLVED: To enable a field-effect transistor to be provided whose channel width is as small as possible, while the size and shape of the channel is controlled as much as possible from being varied. SOLUTION: The production process for the field-effect transistor has the steps of forming a mask 9 as an insulating film onto a semiconductor substrate 4 having on its upper surface a semiconductor layer including silicon, processing the semiconductor layer into a mesa shape extending in one direction parallel to the upper surface of the semiconductor substrate by etching using the mask, narrowing the distance between a pair of lateral sides extending in one direction of the semiconductor layer and facing each other and planarizing the lateral sides by doing heat treatment in a hydrogen atmosphere, forming a gate insulating film 12 covering the semiconductor layer whose sides are planarized, forming a gate electrode 13 covering the gate insulating film, and forming a source/drain region on the semiconductor layer on both sides of the gate electrode. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了使通道宽度尽可能小的场效应晶体管能够尽可能地被控制，尽可能地控制通道的尺寸和形状。解决方案：场效应晶体管的制造方法具有以下步骤：在半导体衬底4上形成作为绝缘膜的掩模9，半导体衬底4的上表面具有包括硅的半导体层，将半导体层加工成台面形状通过使用掩模的蚀刻在平行于半导体衬底的上表面的一个方向上延伸，缩小在半导体层的一个方向上延伸并且彼此面对的一对横向侧之间的距离，并且通过进行热处理来平坦化侧面形成覆盖半导体层的栅极绝缘膜12，栅极绝缘膜12的侧面被平坦化，形成覆盖栅极绝缘膜的栅电极13，并且在栅极两侧的半导体层上形成源极/漏极区域。版权所有（C）2009，JPO＆INPIT

124. 发明专利

JP2009078943A Method for joining silicon carbide ceramic material 有权
标题翻译：陶瓷陶瓷材料的加工方法
公开(公告)号：JP2009078943A
公开(公告)日：2009-04-16
申请号：JP2007248774
申请日：2007-09-26
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ARAI ATSUSHI
IPC分类号： C04B37/00
摘要： PROBLEM TO BE SOLVED: To provide a method for joining silicon carbide ceramic materials, even in silicon carbide ceramic materials with a complicated shape having pores, grooves or the like, which can obtain a joined body without clogging the pores, grooves or the like by a joining material.
SOLUTION: When the silicon carbide ceramic materials are joined using a silicon-containing brazing filler metal, an oxide film is beforehand deposited on the faces to be joined in the silicon carbide ceramic materials by a heat oxidation process, a CVD process or a plasma oxidation process, and joining is performed in such a manner that a brazing filler metal is interposed between the faces to be joined.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于接合碳化硅陶瓷材料的方法，即使在具有孔，槽等的复杂形状的碳化硅陶瓷材料中，其可以获得接合体而不堵塞孔，槽或类似于接合材料。解决方案：当使用含硅钎料金属将碳化硅陶瓷材料接合时，通过热氧化工艺，CVD工艺或CVD方法预先将氧化膜沉积在待接合碳化硅陶瓷材料的表面上等离子体氧化处理，并且以这样的方式进行接合，即在待接合的面之间插入钎料。版权所有（C）2009，JPO＆INPIT

125. 发明专利

JP4246348B2 Gas seal structure of molten metal injection nozzle 有权
公开(公告)号：JP4246348B2
公开(公告)日：2009-04-02
申请号：JP2000024136
申请日：2000-02-01
申请人：コバレントマテリアル株式会社
发明人：和志崎田 , 修森田 , 浩二榎本
IPC分类号： B22D11/10 , B22D11/115 , B22D41/50 , B22D41/58

126. 发明专利

JP2009070872A Compound semiconductor substrate 审中-公开
标题翻译：化合物半导体基板
公开(公告)号：JP2009070872A
公开(公告)日：2009-04-02
申请号：JP2007234972
申请日：2007-09-11
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ABE YOSHIHISA , KOMIYAMA JUN , SUZUKI SHUNICHI , OISHI KOJI , YOSHIDA AKIRA , NAKANISHI HIDEO
IPC分类号： H01L21/205 , H01L33/32 , H01L33/34
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate capable of increasing the film thickness of a nitride semiconductor single crystal layer while suppressing the occurrence of cracks in the nitride semiconductor single crystal layer, crystal defects or the like. SOLUTION: The compound semiconductor substrate has a first intermediate layer 110 formed on an Si single crystal substrate 100 having a crystal plane orientation of ä111}. In the layer 110, a first metal compound layer 110a formed of one of TiC, TiN, VC and VN, and a second metal compound layer 110b formed of one of compounds different from the compound of the first metal compound layer 110a out of TiC, TiN, VC and VN are laminated on each other. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供能够提高氮化物半导体单晶层的膜厚，同时抑制氮化物半导体单晶层中的裂纹的发生，晶体缺陷等的化合物半导体基板。解决方案：化合物半导体衬底具有在晶体取向为ä111}的Si单晶衬底100上形成的第一中间层110。在层110中，由TiC，TiN，VC和VN中的一种形成的第一金属化合物层110a和由与TiC中的第一金属化合物层110a的化合物不同的化合物之一形成的第二金属化合物层110b， TiN，VC和VN彼此层叠。版权所有（C）2009，JPO＆INPIT

127. 发明专利

JP2009065082A Compound semiconductor substrate 审中-公开
标题翻译：化合物半导体基板
公开(公告)号：JP2009065082A
公开(公告)日：2009-03-26
申请号：JP2007233818
申请日：2007-09-10
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： KOMIYAMA JUN , YOSHIDA AKIRA , OISHI KOJI , ABE YOSHIHISA , SUZUKI SHUNICHI , NAKANISHI HIDEO
IPC分类号： H01L21/20 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate having a nitride semiconductor single crystal layer suitable for a high speed and high breakdown voltage device by controlling carriers remaining in a compound semiconductor single crystal layer.
SOLUTION: On an Si single crystal substrate 1, a 3C-SiC single crystal buffer layer 2 with a thickness of 0.05-2 μm containing at least any one impurity element out of B, Al, V, Ni, Fe, Mg, Pt, Cr, Mo, W, Ta, Nb, Sc, Ti, Au, Co and Cu by 10
14 -10
21 /cm
3 , and a GaN single crystal buffer layer 3 with a thickness of 0.05-5 μm containing at least any one impurity element out of C, V, Ni, Fe, Mg, Pt, Cr, Mo, W, Ta, Nb, Sc, Ti, Au, Co and Cu by 10
14 -10
21 /cm
3 are laminated sequentially.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：通过控制残留在化合物半导体单晶层中的载流子，提供具有适用于高速和高击穿电压器件的氮化物半导体单晶层的化合物半导体衬底。解决方案：在Si单晶衬底1上，含有至少含有B，Al，V，Ni，Fe，Mg中的任何一种杂质元素的厚度为0.05-2μm的3C-SiC单晶缓冲层2 ，Pt，Cr，Mo，W，Ta，Nb，Sc，Ti，Au，Co和Cu中的至少一种。以及包含C，V，Ni，Fe，Mg，Pt，Cr，Mo，W，Ta，Nb中的至少一种杂质元素的厚度为0.05-5μm的GaN单晶缓冲层3， Sc，Ti，Au，Co和Cu依次层叠10×SP 14 / SP 3 -10 / SP 3 / cm 3。版权所有（C）2009，JPO＆INPIT

128. 发明专利

JP2009057270A Method of raising silicon single crystal 审中-公开
标题翻译：提高硅单晶的方法
公开(公告)号：JP2009057270A
公开(公告)日：2009-03-19
申请号：JP2008153677
申请日：2008-06-12
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： MINAMI TOSHIRO
IPC分类号： C30B15/00 , C30B29/06
摘要： PROBLEM TO BE SOLVED: To provide a method of raising silicon single crystal in which a rate of variability of a neck diameter is controlled within a predetermined range, and translocation in the neck can be eliminated at an early stage in cultivation of silicon single crystal by a Czochralski method.
SOLUTION: The method of raising silicon single crystal comprises: dipping seed crystal into a raw material silicon melt and pulling up; cultivating a neck; and sequentially increasing the diameter to cultivate single crystal of a predetermined crystal diameter, and is characterized in that the neck diameter is made to increase and decrease and neck cultivation is performed, in that case when a value which divides a neck diameter difference (A-B) between adjoining inflection points P
1 and P
2 of the fluctuating neck diameter by a neck length L between the inflection points is made a neck diameter variation rate, the neck diameter variation rate is made 0.05 or more and less than 0.5.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决问题的方法：提供一种提高将颈部直径变异率控制在预定范围内的单晶硅的方法，并且可以在早期阶段消除颈部易位单晶由Czochralski法。解决方案：提高硅单晶的方法包括：将晶种浸入原料硅熔体并拉起; 培养脖子并依次增加直径以培养预定晶体直径的单晶，其特征在于使颈部直径增大和减小，并进行颈部培养，在这种情况下，当将颈部直径差（AB）在颈部直径的变化颈部的相邻拐点P＆lt; SB＆gt; 1＆lt; SB＆gt; 2＆lt; / SB＆gt;之间，使颈部直径变化率，颈部直径变化率为0.05以上且小于0.5。版权所有（C）2009，JPO＆INPIT

129. 发明专利

JP2009057232A Silicon single crystal growing method and its apparatus 审中-公开
标题翻译：硅晶单晶生长方法及其设备
公开(公告)号：JP2009057232A
公开(公告)日：2009-03-19
申请号：JP2007225013
申请日：2007-08-31
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： HISAICHI TOSHIO
IPC分类号： C30B29/06 , C30B15/22
摘要： PROBLEM TO BE SOLVED: To simply suppress solidification of silicon easily generated from the inner wall of a quartz crucible in pull-up growing of a silicon single crystal by MCZ method using a cusp magnetic field.
SOLUTION: A silicon melt 12 is formed in a quartz crucible 13 with a main chamber interior 11 of a silicon single crystal growing apparatus 10 put in an inert gas atmosphere. A cusp magnetic field is generated by electromagnetic coils 20, 21 and the magnetic field is applied perpendicularly to the side wall surface and the bottom surface of the quartz crucible 13, while after a seed crystal 26 attached to a seed chuck 27 is contacted with the silicon melt 12, a pull-up shaft 25 is pulled up at a prescribed speed. The quartz crucible 13 is rotated in varied speeds by adding a periodical pulsating increase/decrease to a standard rotation speed by a rotation/up and down-driving device 23 to rotate and up/down-drive a support shaft 22. A driving control section 24 controls the speed-varied rotation operation of the rotation/up and down-driving device 23.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过使用尖点磁场的MCZ方法，通过硅单晶的上拉生长，简单地抑制从石英坩埚的内壁容易产生的硅的固化。解决方案：在硅单晶生长装置10的主室内部11放置在惰性气体气氛中的石英坩埚13中形成硅熔体12。尖角磁场由电磁线圈20,21产生，并且垂直于石英坩埚13的侧壁表面和底表面施加磁场，同时在连接到种子卡盘27的晶种26与硅熔体12，上拉轴25以规定的速度被拉起。石英坩埚13通过旋转/上下驱动装置23将标准旋转速度的周期性脉动增加/减小加以旋转和上/下驱动支撑轴22，以不同的速度旋转。驱动控制部分 24控制旋转/上下驱动装置23的速度变化的旋转操作。版权所有：（C）2009，JPO＆INPIT

130. 发明专利

JP4222591B2 Grindstone and processing forming method using the same of the ring-shaped member, and a method of cooling medium supply grindstone of the ring-shaped member 有权
公开(公告)号：JP4222591B2
公开(公告)日：2009-02-12
申请号：JP2002016586
申请日：2002-01-25
申请人：コバレントマテリアル株式会社
发明人：真弘久保田 , 能徳重野 , 英一金丸
IPC分类号： B24B55/02 , B24D7/18 , B24D7/00

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