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1. 发明专利

JP2000029692A CENTRAL PROCESSOR 失效
公开(公告)号：JP2000029692A
公开(公告)日：2000-01-28
申请号：JP13977299
申请日：1999-05-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/355 , G06F9/34
摘要： PROBLEM TO BE SOLVED: To decrease program capacity or increase the efficiency of a program memory and to reduce the system cost by adopting a fixed-length instruction format whose bit number is less than the maximum data word length supplied to an instruction executing means. SOLUTION: An instruction register IR1 holds an instruction present at an instruction decoding means. The decoding results of a source register decoder SRD and a destination register decoder DRD are used to specify which of general register R0H, R0L to R15H, and R15L included in an execution part EXEC is selected. With a data transfer instruction, data stored in the address obtained by adding a value of displacement and the value of an address stored in a program counter are transferred to one of registers. In this case, the fixed-length instruction format whose bit number is less than the maximum data word length supplied to the instruction execution means is adopted.

2. 发明专利

JPH10105276A MICROCOMPUTER DEVICE 失效
公开(公告)号：JPH10105276A
公开(公告)日：1998-04-24
申请号：JP26167996
申请日：1996-10-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： AIZAWA TATSUYA , UNO SHIGEO , MARUYAMA SHIGENORI , NISHIHARA TAKAFUMI , FUKADA KAORU
IPC分类号： G06F1/06 , G06F1/14
摘要： PROBLEM TO BE SOLVED: To reduce a program amount with abstract and functional meaning of a program remained by setting a numeric value N to a cycle register and having a structure of outputting a waveform whose cycle is N and duty is M/N when a numeric value M is set to an interior division register. SOLUTION: When a numeric value N is set to a cycle register CYCR 24 and a numeric value M is set to an interior division register DVR 21, a waveform whose cycle is N and duty is M/N is formed and it is outputted externally by outputting one externally by compare match between a CYCR value of the register CYCR 24 and a UCNT value of an upcounter UCNT 18 and outputting zero externally by compare match between a DVR value of the register DVR 21 and the UCNT value of the upcounter UNCT 18. An application program becomes extremely simple because a cycle is a setting value to the cycle register and duty is (setting value to the interior division register/setting value to the cycle register).

3. 发明专利

JPH04262568A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04262568A
公开(公告)日：1992-09-17
申请号：JP4447291
申请日：1991-02-15
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK
发明人： OCHIAI TATSUO , MIYAZAKI KENJI , NAKADA KUNIHIKO , FUKADA KAORU
IPC分类号： G01R31/28 , H01L21/66 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092
摘要： PURPOSE:To provide a technique for accurately diagnosing an operation of a P-channel type MOSFET contained in a bus driver coupled to a bus to be precharged. CONSTITUTION:An N-channel type MOSFET 15 is provided. The MOSFET 15 is turned ON in synchronization with an initial clock CLK of a bus cycle thereby to discharge an inner data bus BUS, and hence the bus BUS is set to a low level. Accordingly, a high level is output from a bus driver 17b in a peripheral functional module 19 in this state. The state of the bus BUS at that time is checked by a CPU 18 thereby to diagnose an operation of a P- channel type MOSFET included in the driver 17b.

4. 发明专利

JP2001067219A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JP2001067219A
公开(公告)日：2001-03-16
申请号：JP2000212452
申请日：2000-07-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/34 , G06F9/355 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To prevent the use of immediate data and absolute address specification from being restricted even if the number of bits of a fixed-length instruction format is less than the length of a data word by adopting the fixed-length instruction format whose number of bits is less than maximum data word length. SOLUTION: A microcomputer has RISC type architecture and also has an instruction format of fixed length. A bus where data and instructions are transferred has 32-bit constitution. The instructions, on the other hand, are in 16-bit fixed-length instruction format. This 16-bit fixed-length instruction format is employed for 32-bit data word length and then where an instruction border is present can be decided before a last instruction is completed as well as a RISC machine having a conventional 32-bit fixed-length instruction format since the instruction format has the fixed length. Consequently, such problem that a memory needs to be increased in circuit scale can be evaded.

5. 发明专利

JPH01218129A A/D CONVERSION CIRCUIT 失效
公开(公告)号：JPH01218129A
公开(公告)日：1989-08-31
申请号：JP4206188
申请日：1988-02-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： FUKADA KAORU , NAGASAKI NOBUTAKA , MATSUURA HIROYUKI
IPC分类号： H03M1/10
摘要： PURPOSE:To shorten test time and to eliminate the need for the tester side to read the output of the result of A/D conversion on each occasion and to compare it with an expected value by providing a deciding circuit comparing the output of result of conversion of the A/D conversion circuit and the expected value. CONSTITUTION:The deciding circuit comparing the output of result of conversion of the A/D conversion circuit and the expected value is provided. The output of the result of conversion of the A/D conversion circuit ADC is stored in a register R0 as a storage circuit. In order to reduce the testing time of the A/D conversion circuit, a digital comparator COM and expected value storage registers R1, R2...R2 are provided. The expected values 2...2 are supplied in the lump from an external terminal to the registers R1, R2...R2 . Thus, it is not required for the tester side to read the output of result of A/D conversion on each occasion and to compare it with the expected value and the test time is shortened.

6. 发明专利

JPH06150023A MICROCOMPUTER AND SYSTEM THEREOF 失效
公开(公告)号：JPH06150023A
公开(公告)日：1994-05-31
申请号：JP32259892
申请日：1992-11-06
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , FUKADA KAORU , WATABE MITSURU , NOGUCHI YOSHIKI , MATSUBARA KIYOSHI , MOCHIZUKI ISAMU , SUZUKAWA KAZUFUMI , MASUMURA SHIGEKI , AKAO YASUSHI , SAKAKIBARA EIJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/42 , G06F15/78
摘要： PURPOSE:To flexibly deal with required system construction by adopting an interface for a dynamic RAM and an interface for a memory such as a static RAM and a peripheral circuit to the microcomputer. CONSTITUTION:This microcomputer is provided with strobe signal output terminals CASH, CASL and RAS for the dynamic RAM and chip select signal output terminals CSO-CS6 for outputting chip select signals parallelly to respective outputs. Then, an address output terminal can output non-multiplexed address signals or address signals multiplexed as needed, and the input/output terminal of data is provided for selectively outputting the address signals so as to cope with the multibus system interface. Thus, the interface for the dynamic RAM and the interface for the memory such as the static RAM and the other peripheral circuit are adopted to the microcomputer.

7. 发明专利

JPH05197546A MICROCOMPUTER AND DIVIDING CIRCUIT 失效
公开(公告)号：JPH05197546A
公开(公告)日：1993-08-06
申请号：JP15452592
申请日：1992-05-21
申请人： HITACHI LTD , HITACHI MICOM SYST KK , HITACHI VLSI ENG
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/28 , G06F7/483 , G06F7/52 , G06F7/527 , G06F7/535 , G06F7/537 , G06F9/30 , G06F9/302 , G06F9/305 , G06F9/318 , G06F9/32 , G06F9/38
摘要： PURPOSE:To decrease program capacity or improve the utilization efficiency of a program memory by employing a fixed length instruction format which is smaller in the number of bits than the maximum length of data words supplied to an instruction executing means. CONSTITUTION:The microcomputer has RISC(reduced instruction set type computer) type architecture and has the fixed length instruction format. When data and instructions are transferred, a bus, e.g. an internal data bus IDB is of 32-bit constitution, but the instructions are in 16-bit fixed length instruction format. Then 16-bit instruction buffers (instruction queue) IRH and IRL store the instructions, one by one, and the instructions are loaded respectively in a single instruction fetch cycle. The instructions are transferred in 32-bit units through the internal data bus IDB and then loaded in an instruction register IR1 through a multiplexer MPX. Then the 16-bit instruction register IR1 holds the instructions present in an instruction decoding stage.

8. 发明专利

JP2003330907A Microcomputer system 审中-公开
标题翻译：微型计算机系统
公开(公告)号：JP2003330907A
公开(公告)日：2003-11-21
申请号：JP2003113567
申请日：2003-04-18
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MASUMURA SHIGEKI , NAKAMURA HIDEO , NOGUCHI YOSHIKI , KAWASAKI SHUNPEI , FUKADA KAORU , AKAO YASUSHI
IPC分类号： G06F15/78 , G06F13/38
摘要： PROBLEM TO BE SOLVED: To provide a bus operating method capable of easily changing a bus interface specification by increasing effective operation speeds of a bus, and a memory and peripheral function units connected to the bus, in a microcomputer system. SOLUTION: An access operation through buses 113 and 114 with bus masters 101 and 102 connected is executed in a pipeline manner, and control of the pipeline execution is carried out by an exclusive bus controller 111. An access delaying the pipeline operation is executed by buses 123 and 124 of a lower tier connected through a buffer means 112, and by a bus controller 121 exclusively used for the lower tier. Therefore, the bus band for access is improved, and bus interfaces having various specifications, and buses allowing parallel execution can easily be structured. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种总线操作方法，其能够通过在微计算机系统中增加总线的有效操作速度以及连接到总线的存储器和外围功能单元来容易地改变总线接口规范。解决方案：以流水线方式执行通过连接有总线主机101和102的总线113和114的访问操作，并且由专用总线控制器111执行流水线执行的控制。延迟流水线操作的访问是由通过缓冲装置112连接的下层的总线123和124执行，并且由专用于下层的总线控制器121执行。因此，改善了用于访问的总线频带，并且可以容易地构造具有各种规格的总线接口和允许并行执行的总线。版权所有（C）2004，JPO

9. 发明专利

JP2001044373A COMPUTER-READABLE STORAGE MEDIUM, LOGIC MODULE, AND SEMICONDUCTOR AND TESTING METHOD THEREFOR 失效
公开(公告)号：JP2001044373A
公开(公告)日：2001-02-16
申请号：JP21990199
申请日：1999-08-03
申请人： HITACHI LTD
发明人： FUKADA KAORU
IPC分类号： H01L21/822 , G01R31/28 , G01R31/3185 , G06F17/50 , H01L21/82 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a testing technology of a semiconductor device, which restricts the overhead of an area to a minimum and can make a signal propagate in parallel to testing by a method, wherein the signal is bypassed by utilizing an existent data path in an IP core. SOLUTION: This device is constituted by an existent logic integrated circuit, as an IP core 1 of a logic module put together as a functional block, comprising input terminals 2a to 2c, output terminals 3a to 3c, combination circuits 4a to 4h, storage circuits 5a to 5k, data paths 6a to 6d, and like, a testing signal path 7 of test mode signal connected to each of the combination circuits 4a to 4h, a testing storage circuit 8 for storing a signal of the data path 6b, a switching circuit for testing 9 for switching the data path 6b to the path 6c, and the like, when testing, a bypass mode is set according to a test mode signal, and a signal is make to pass through, in parallel from the input terminals 2a to 2c to the output terminals 3a to 3c via the data paths 6a to 6c.

10. 发明专利

JPH11102286A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JPH11102286A
公开(公告)日：1999-04-13
申请号：JP15814398
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method for division with which a correct quotient can be easily found without detecting whether the partial remainder is '0' or not for each step of division for finding the quotient bit even when a dividend is negative. SOLUTION: When a dividend X is negative in the coded division expressed as Y (quotient) = X (dividend) ÷ 3 (divisor), for example, preprocessing is performed to define a value (X-1) subtracting '1' from the dividend X as a dividend. The preprocessing is processing for conceptionally shifting the coordinate axis of the quotient Y to left for '1'. The processing of division is performed in the shifting state. Thus, it is not necessary to discriminate whether the partial remainder is '0' or not conventionally every time in the middle of arithmetic processing and a hardware for that discrimination is unnecessitated as well. When finding the exact remainder, the found remainder is finally corrected.

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