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1. 发明授权

EP3992967B1 MEMORY PACKAGE, STORAGE DEVICE INCLUDING MEMORY PACKAGE, AND STORAGE DEVICE OPERATING METHOD 有权
公开(公告)号：EP3992967B1
公开(公告)日：2024-10-30
申请号：EP21179017.5
申请日：2021-06-11
IPC分类号： G11C5/02 , G11C7/10 , G06F13/40
CPC分类号： G11C7/1012 , G11C5/025

2. 发明授权

EP3975187B1 MEMORY DEVICE FOR COLUMN REPAIR 有权
公开(公告)号：EP3975187B1
公开(公告)日：2024-10-16
申请号：EP21183755.4
申请日：2021-07-05
IPC分类号： G11C29/00 , G11C5/02 , G11C7/10 , G11C16/26 , G11C29/12 , G11C29/38 , G11C29/44
CPC分类号： G11C29/81 , G11C29/816 , G11C29/82 , G11C29/844 , G11C29/846 , G11C29/4401 , G11C29/38 , G11C29/1201 , G11C2029/120620130101 , G11C2029/120420130101 , G11C5/025 , G11C7/1057 , G11C7/106 , G11C7/1063 , G11C16/26 , G11C29/702 , G11C2211/564320130101 , G11C2211/564420130101 , G11C29/804

3. 发明公开

EP4394771A1 FLASH MEMORY ARRAY, AND WRITE METHOD AND ERASURE METHOD THEREFOR 审中-实审
公开(公告)号：EP4394771A1
公开(公告)日：2024-07-03
申请号：EP22860607.5
申请日：2022-08-25
申请人： Beijing Panxin Microelectronics Technology Co., Ltd.
发明人： JIANG, Jiayong , SHI, Zhendong
IPC分类号： G11C5/02 , G11C7/12
CPC分类号： G11C5/02 , G11C7/12
摘要： Provided in the present disclosure are a flash memory array, and a write method and erasure method therefor. The flash memory array according to the present disclosure comprises : a plurality of flash memory cells, which are arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups, which extend in the row direction; and a plurality of bit line groups, which extend in the column direction, wherein flash memory cell pairs are arranged at intersection points of the word line groups and the bit line groups, and the flash memory cell pair comprises a first flash memory cell and a second flash memory cell, which are adjacent in the row direction and share the same bit line group. By means of the flash memory array according to the present disclosure, the arrangement density of bit lines can be improved while the size of the array is not increased, and the bit line parasitic resistance can be reduced. In addition, compared with a flash memory array in the prior art, the flash memory array according to the present disclosure also has a better process compatibility and scaling characteristic. The write method for a flash memory array of the present disclosure has the advantages of a low operation power consumption and a fast programming speed, which is conducive to improving the number of concurrently written flash memory cells, thereby increasing the data writing throughput rate of a memory. The erasure method for a flash memory array of the present disclosure can improve a threshold voltage window and enhance the storage reliability, and also has the advantages of a low operation power consumption and a fast erasure speed.

4. 发明公开

EP4390930A1 SRAM AVEC MISE EN VEILLE DE SECTEUR DEDIE AU PUF 审中-实审
公开(公告)号：EP4390930A1
公开(公告)日：2024-06-26
申请号：EP23218362.4
申请日：2023-12-19
申请人： Commissariat à l'énergie atomique et aux énergies alternatives
发明人： NOEL, Jean-Philippe , GERBAUD, Merlin , GIRAUD, Bastien , CIAMPOLINI, Lorenzo
IPC分类号： G11C7/24 , G06F21/79 , G11C7/20 , G11C11/419 , G11C5/02 , G11C7/10 , G11C7/18 , G11C8/08 , G11C29/24 , G11C29/44
CPC分类号： G11C7/24 , G11C7/20 , G11C11/419 , G11C8/08 , G11C7/1069 , G11C7/18 , G11C5/025 , G11C29/24 , G11C2029/440220130101 , G06F21/79
摘要： Dispositif de mémoire statique à accès aléatoire comprenant une matrice mémoire (M) dotée de cellules mémoires SRAM chacune desdites cellules dudit ensemble comprenant un premier noeud (NT) de stockage et un deuxième noeud (NF) de stockage, le dispositif étant doté en outre d'un circuit de commande (160, 180, 120, T1) desdites cellules configuré pour, après une mise sous tension de la matrice (M), mettre la matrice dans un premier mode de fonctionnement dans lequel un premier ensemble (E1) de cellules situé dans une première zone (Z1) de la matrice dans un état dit « métastable » pour lequel le premier noeud (NT) de stockage et ledit deuxième noeud (NF) de stockage sont mis à des potentiels égaux ou sensiblement égaux tandis qu'un deuxième ensemble (E2) de cellules situé dans une deuxième zone (Z2) de la matrice (M) distincte de la première zone (Z1) ont leurs premier noeud (NT) et deuxième noeud (NT) respectifs à des potentiels respectifs différents et correspondant à un état logique donné entre un état bas et un état haut et à un état logique complémentaire dudit état donné.

5. 发明公开

EP4376008A1 DISTRIBUTED WRITE DRIVER FOR CROSSBAR MEMORY 审中-公开
公开(公告)号：EP4376008A1
公开(公告)日：2024-05-29
申请号：EP22208717.3
申请日：2022-11-22
申请人： Imec VZW
发明人： Gupta, Mohit
IPC分类号： G11C11/16 , G11C13/00 , G11C29/02 , G11C5/02 , G11C5/06 , G11C7/12 , G11C8/08 , G11C29/04
CPC分类号： G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C11/1655 , G11C11/1657 , G11C5/063 , G11C5/025 , G11C8/08 , G11C7/12 , G11C29/021 , G11C29/028 , G11C2029/040920130101
摘要： The present disclosure relates to a write driver and a method for operating the write driver for a memory device. The write driver is connected to a memory line of the memory device. Multiple memory cells of the memory device are connected to the memory line at different distances from the write driver. The operating method comprises controlling the write driver to provide a smaller amount of current for accessing a first memory cell of the memory cells, and controlling the write driver to provide a larger amount of current for accessing a second memory cell of the memory cells. Thereby, the first memory cell is connected to the memory line at a smaller distance to the write driver than the second memory cell.

6. 发明授权

EP3955295B1 SEMICONDUCTOR STRUCTURE AND PREHEATING METHOD THEREFOR 有权
公开(公告)号：EP3955295B1
公开(公告)日：2024-05-01
申请号：EP20926529.7
申请日：2020-11-25
IPC分类号： G11C7/04 , G11C7/20 , G11C11/4072 , G11C5/02 , G11C5/04 , G11C11/4076 , H01L25/065 , H01L25/16 , H01L25/18
CPC分类号： H01L25/18 , G11C7/04 , G11C5/04 , G11C11/4072 , G11C11/4076 , H01L25/16 , H01L25/0657 , H01L25/0652 , H01L2225/0654120130101 , H01L2225/0658920130101 , G11C7/20 , G11C5/025

7. 发明公开

EP4307372A3 STACKED MEMORY DICE FOR COMBINED ACCESS OPERATIONS 审中-实审
公开(公告)号：EP4307372A3
公开(公告)日：2024-03-20
申请号：EP23212532.8
申请日：2020-02-06
申请人： Micron Technology, Inc.
发明人： GANS, Dean D.
IPC分类号： G11C5/06 , G11C5/02 , G11C5/04 , G06F3/06 , G06F13/42 , G06F12/06 , G06F12/0862 , G06F13/16 , G11C7/10 , H01L25/065
摘要： Methods, systems, and devices for stacked memory dice and combined access operations are described. A device may include multiple memory dice. One die may be configured as a master, and another may be configured as a slave. The master may communicate with a host device. A slave may be coupled with the master but not the host device. The device may include a first die (e.g., master) and a second die (e.g., slave ). The first die may be coupled with a host device and configured to output a set of data in response to a read command. The first die may supply a first subset of the data and obtain a second subset of the data from the second die. In some cases, the first die may select, based on a data rate, a modulation scheme (e.g., PAM4, NRZ, etc.) and output the data using the selected modulation scheme.

8. 发明公开

EP4235512A3 SYSTEM AND METHOD FOR IMPLEMENTING CONFIGURABLE CONVOLUTED NEURAL NETWORKS WITH FLASH MEMORIES 审中-实审
公开(公告)号：EP4235512A3
公开(公告)日：2023-11-01
申请号：EP23179955.2
申请日：2018-08-22
申请人： Silicon Storage Technology Inc.
发明人： TIWARI, Vipin , DO, Nhan
IPC分类号： G06N3/045 , G06N3/048 , G06N3/065 , G11C5/02 , G11C7/10 , G11C16/04 , G11C16/24 , H10B41/30
摘要： A memory array with memory cells arranged in rows and columns. Each memory cell includes source and drain regions with a channel region there between, a floating gate disposed over a first channel region portion, and a second gate disposed over a second channel region portion. A plurality of bit lines each extends along one of the columns and is electrically connected to the drain regions of a first group of one or more of the memory cells in the column and is electrically isolated from the drain regions of a second group of one or more of the memory cells in the column. A plurality of source lines each is electrically connected to the source regions memory cells in one of the columns or rows. A plurality of gate lines each is electrically connected to the second gates of memory cells in one of the columns or rows.

9. 发明授权

EP3579236B1 NON-VOLATILE MEMORY DEVICE AND ERASING METHOD OF THE SAME 有权
公开(公告)号：EP3579236B1
公开(公告)日：2023-09-13
申请号：EP19177925.5
申请日：2019-06-03
发明人： LEE, Ji-Young , RHO, Young-sik , PARK, Il-han
IPC分类号： G11C16/16 , G11C16/34 , G11C11/56 , G11C16/04 , G11C5/02

10. 发明公开

EP4128233A1 MEMORY SUB-SYSTEM MANUFACTURING MODE 审中-实审
公开(公告)号：EP4128233A1
公开(公告)日：2023-02-08
申请号：EP21779191.2
申请日：2021-03-19
申请人： Micron Technology, Inc.
发明人： HIEB, Adam J.
IPC分类号： G11C5/02 , G11C5/04 , G11C5/06 , G06F13/16

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