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2. 发明公开

EP4362022A1 COLUMN REPAIR IN A MEMORY SYSTEM USING A REPAIR CACHE 审中-公开
公开(公告)号：EP4362022A1
公开(公告)日：2024-05-01
申请号：EP23203321.7
申请日：2023-10-12
申请人： NXP USA, Inc.
发明人： Choy, Jon Scott , Strauss, Timothy , Storms, Maurits Mario Nicolaas , Hume, Christopher Nelson , Wagemans, Silvia
IPC分类号： G11C29/00 , G11C7/10 , G11C11/16 , G11C29/44
CPC分类号： G11C29/789 , G11C29/76 , G11C29/816 , G11C29/846 , G11C29/4401 , G11C2029/440220130101 , G11C29/808 , G11C29/80 , G11C11/1655 , G11C7/1066 , G11C7/1069
摘要： A main memory includes a first plurality of input/outputs (I/Os) configured to output data stored in the main memory in response to a read access request. A first portion of the first plurality of IOs provides user read data in response to the read access request and a second portion of the first plurality of IOs provides candidate replacement IOs. Repair circuitry is configured to selectively replace one or more IOs of the first portion of IOs using one or more of the candidate replacement IOs of the second portion of IOs to provide repaired read data in response to the read access request in accordance with repair mapping information corresponding to an access address of the read access request. A static random access memory (SRAM) stores repair mapping information, and a repair cache stores cached repair mapping information from the SRAM for address locations of the main memory.

3. 发明授权

EP1717814B1 SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE CONTROL METHOD 有权
标题翻译：半导体存储装置及半导体存储器设置控制方法
公开(公告)号：EP1717814B1
公开(公告)日：2012-09-19
申请号：EP04713217.0
申请日：2004-02-20
申请人： Spansion LLc , Spansion Japan Limited
发明人： NAGAO, Mitsuhiro, SPANSION JAPAN LIMITED
IPC分类号： G11C29/00 , G11C7/10
CPC分类号： G11C7/1051 , G11C5/025 , G11C7/1027 , G11C7/1042 , G11C29/846 , G11C2207/107

4. 发明授权

EP1367599B1 Redundancy circuit and method for semiconductor memory devices 有权
标题翻译：冗余电路和方法，用于半导体存储器
公开(公告)号：EP1367599B1
公开(公告)日：2011-04-06
申请号：EP03253297.0
申请日：2003-05-27
申请人： STMicroelectronics, Inc.
发明人： McClure, David C.
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/846

5. 发明公开

EP1986233A2 On-chip reconfigurable memory 失效
标题翻译： Rekonfigurierbarer芯片旁观者
公开(公告)号：EP1986233A2
公开(公告)日：2008-10-29
申请号：EP08006005.6
申请日：1998-04-03
申请人： Leedy, Glenn, J.
发明人： Leedy, Glenn, J.
IPC分类号： H01L25/065 , H01L21/768 , H01L27/06 , H01L27/108 , H01L21/822 , H01L27/105 , H01L21/603 , G11C29/00
CPC分类号： H01L27/10897 , G11C5/02 , G11C5/025 , G11C5/04 , G11C29/44 , G11C29/81 , G11C29/846 , G11C29/848 , H01L23/481 , H01L25/18 , H01L27/0688 , H01L27/105 , H01L2224/29109 , H01L2224/29111 , H01L2224/29116 , H01L2224/29118 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29166 , H01L2224/29169 , H01L2224/8083 , H01L2225/06541 , H01L2924/01079 , Y10S438/977 , H01L2924/00014
摘要： An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.
摘要翻译：公开了一种片上可重构存储器，包括：多个数据线，多条栅极线，存储器单元阵列，每个存储单元存储数据值，并且包括用于将该数据值耦合到所述数据线之一的电路响应于所述栅线之一的选择，用于使栅极线用于存储器操作的栅极线选择电路，所述栅极线选择电路包括可编程门以接收一个或多个所述栅极线的地址分配，所述地址用于确定为每个编程的地址分配选择哪个所述栅极线的分配以及用于确定至少一个所述存储单元是有缺陷的控制器，并且用于在至少一个实例中改变所述栅极线的所述地址分配以消除参考该栅极线导致该缺陷存储单元将数据值耦合到所述数据线之一。

6. 发明公开

EP1376609A3 Efficient column redundancy techniques 有权
标题翻译：有效的列冗余程序
公开(公告)号：EP1376609A3
公开(公告)日：2008-07-16
申请号：EP03014061.0
申请日：2003-06-23
申请人： Broadcom Corporation
发明人： Winograd, Gil I. , Terzioglu, Esin
IPC分类号： G11C29/00 , G11C11/417
CPC分类号： G11C29/808 , G06F13/4086 , G11C7/18 , G11C11/41 , G11C11/419 , G11C29/846 , G11C29/848
摘要： The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder (2712) and a multi-bank memory (2710). The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit (2716) adapted to complete a word for a failing bank in the multi-bank memory.

7. 发明公开

EP1369878A1 System for testing a group of functionally independent memories and for replacing failing memory words 审中-公开
标题翻译：用于测试一组功能独立的存储器和用于替换有缺陷的存储器字的装置
公开(公告)号：EP1369878A1
公开(公告)日：2003-12-10
申请号：EP02012318.8
申请日：2002-06-04
申请人： Infineon Technologies AG
发明人： Borri, Simone , Kirmser, Stephane
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/14 , G11C29/846
摘要： System for testing a group of functionally independent memories (102) and for replacing failing memory words of the group of functionally independent memories (102) by redundant memory words, comprising: a redundancy means (108) including at least one array of redundant memory words (108a) and address registers (108b) connected to the at least one array of redundant memory words (108a); a test means (114); a group of first multiplexers (110) following the test means (114) and preceding the memories (102) and the at least one array of redundant memory words (108a); and a group of second multiplexers (112) following the memories (102) and the at least one array of redundant memory words (108a), wherein each second multiplexer (112) is connectable to the test means (114).
摘要翻译：系统用于测试组的功能独立的存储器（102）和用于替换的基团的功能独立的存储器（102）由冗余存储器字的失效存储器字，其包含：一个冗余装置（108）包括的冗余存储器字的至少一个阵列（108A），并连接到的冗余存储器字（108A）的所述至少一个阵列地址寄存器（108B）; 测试装置（114）; 一组第一多路复用器（110）按照所述测试装置（114）的和preceding-存储器（102）和冗余存储器字（108A）的所述至少一个阵列; 和一组第二多路复用器（112）按照与存储器（102）和冗余存储器字，所述至少一个阵列（108A）worin每个第二多路复用器（112）可连接到所述测试装置（114）。

8. 发明公开

EP1365419A1 Self-repair method for non volatile memory device with erasing/programming failure detection, and non volatile memory device therefor 有权
标题翻译：用于与擦除/编程错误检测非易失性存储器件和非易失性存储器设备，用于自修复方法
公开(公告)号：EP1365419A1
公开(公告)日：2003-11-26
申请号：EP02425319.7
申请日：2002-05-21
申请人： STMicroelectronics S.r.l.
发明人： Micheloni, Rino , Losavio, Aldo
IPC分类号： G11C29/00
CPC分类号： G11C29/82 , G11C29/846
摘要： The memory device (20) has a memory block (1), formed by a plurality of standard sectors (15) and a redundancy portion (2); a control circuit (3), which controls programming and erasing of the data of the memory cells; and a correctness verifying circuit (7) for the data stored in the memory cells. The correctness verifying circuit (7) is enabled by the control circuit (3) and generates an incorrect-datum signal in the event of detection of at least one non-functioning cell. The control circuit moreover activates redundancy, enabling the redundancy portion (2) and storing redundancy data in a redundancy-memory stage (5b) in the presence of an incorrect datum. Various solutions are presented that implement column, row and sector redundancy, both in case of erasing and programming.
摘要翻译：所述存储器装置（20）具有存储块（1）中，通过标准的扇区（15）的形成有多个和冗余部（2）; 其控制所述存储器单元的数据的编程和擦除控制电路（3）; 和用于所述数据的正确性验证电路（7）存储在存储器单元中。正确性验证电路（7）由所述控制电路（3）和基因速率不正确的，基准信号在检测到至少一个非功能性细胞的的情况下启用。该控制电路更在激活冗余，使冗余部分（2）和在一个不正确的日期的存在下，在冗余存储器阶段（5b）中存储的冗余数据。各种解决方案都没有实现列，行和部门冗余，无论是在擦除和编程的情况。

9. 发明公开

EP1134659A3 Redundanz-Multiplexer für Halbleiterspeicheranordnung 有权
标题翻译：冗余复用器，用于半导体存储器件
公开(公告)号：EP1134659A3
公开(公告)日：2002-06-05
申请号：EP01104907.9
申请日：2001-02-28
申请人： Infineon Technologies AG
发明人： Nygren, Aaron
IPC分类号： G06F11/20
CPC分类号： G11C29/846
摘要： Die Erfindung betrifft einen Redundanz-Multiplexer, bei dem durch Vergleich der Adressen von zwei in Reihe liegenden Schaltern (14) und gegebenenfalls deren Austausch sichergestellt ist, daß keine fehlerhaften Bitleitungen ausgelesen werden.

10. 发明授权

EP0584832B1 Integrated memory circuit device 失效
标题翻译：集成电路存储器装置
公开(公告)号：EP0584832B1
公开(公告)日：2001-11-28
申请号：EP93113750.9
申请日：1993-08-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Watanabe, Yuji
IPC分类号： G11C11/00 , G06F11/20
CPC分类号： G11C29/846 , G11C7/10

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