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基本信息:
- 专利标题: FLASH MEMORY ARRAY, AND WRITE METHOD AND ERASURE METHOD THEREFOR
- 申请号:EP22860607.5 申请日:2022-08-25
- 公开(公告)号:EP4394771A1 公开(公告)日:2024-07-03
- 发明人: JIANG, Jiayong , SHI, Zhendong
- 申请人: Beijing Panxin Microelectronics Technology Co., Ltd.
- 申请人地址: CN Beijing 100191 Room 1509B, Quantum Ginza No. 23, Zhichun Road Haidian District
- 专利权人: Beijing Panxin Microelectronics Technology Co., Ltd.
- 当前专利权人: Beijing Panxin Microelectronics Technology Co., Ltd.
- 当前专利权人地址: CN Beijing 100191 Room 1509B, Quantum Ginza No. 23, Zhichun Road Haidian District
- 代理机构: Hoffmann Eitle
- 优先权: CN 2110989487 2021.08.26
- 国际申请: CN2022114959 2022.08.25
- 国际公布: WO2023025261 2023.03.02
- 主分类号: G11C5/02
- IPC分类号: G11C5/02 ; G11C7/12
摘要:
Provided in the present disclosure are a flash memory array, and a write method and erasure method therefor. The flash memory array according to the present disclosure comprises : a plurality of flash memory cells, which are arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups, which extend in the row direction; and a plurality of bit line groups, which extend in the column direction, wherein flash memory cell pairs are arranged at intersection points of the word line groups and the bit line groups, and the flash memory cell pair comprises a first flash memory cell and a second flash memory cell, which are adjacent in the row direction and share the same bit line group. By means of the flash memory array according to the present disclosure, the arrangement density of bit lines can be improved while the size of the array is not increased, and the bit line parasitic resistance can be reduced. In addition, compared with a flash memory array in the prior art, the flash memory array according to the present disclosure also has a better process compatibility and scaling characteristic. The write method for a flash memory array of the present disclosure has the advantages of a low operation power consumption and a fast programming speed, which is conducive to improving the number of concurrently written flash memory cells, thereby increasing the data writing throughput rate of a memory. The erasure method for a flash memory array of the present disclosure can improve a threshold voltage window and enhance the storage reliability, and also has the advantages of a low operation power consumption and a fast erasure speed.
IPC结构图谱:
G | 物理 |
--G11 | 信息存储 |
----G11C | 静态存储器 |
------G11C5/00 | 包括在G11C11/00组中的存储器零部件 |
--------G11C5/02 | .存储元件的排列,例如,矩阵形式的排列 |