专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0295409A2 Programmable skew-tolerant array processor architecture 失效
标题翻译： Feldrechner-Architektur的Programmierbareschrägverzerrungstolerante。
公开(公告)号：EP0295409A2
公开(公告)日：1988-12-21
申请号：EP88107075.9
申请日：1988-05-03
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun , Li, Hungwen
IPC分类号： G06F15/06 , G06F13/42
CPC分类号： G06F15/8023 , G06F1/04 , G06F1/08 , G06F1/10
摘要： Using a variable-duration clock, together with programmable duration definition means to alter the clock waveform (8) within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately longer durations for longer data transfers in an array processor of myriad processing elements. There is no need to allow sufficient time in every clock cycle for worst case data transfer between remote processing elements (3).
The clock waveform has three recognizable edges (A,B,C) regardless of loss of sharpness during its travel to the various processing elements. The convention that three skew-sensitive activities, READ, WRITE and OPERAND SUPPLY conform to respectively assigned edges as follows:
A = READ;
B = OPERAND SUPPLY;
C = WRITE (Read next)
The processing elements synchronize with the clock waveform, which is optimized for the instructions of the program being executed. There is no time wasted allowing for worst case data transfers possible in certain instructions but not possible in other instructions.
摘要翻译：使用可变持续时间时钟以及可编程持续时间定义装置在严格规则内改变时钟波形（8），允许编程人员为短时间数据传输安排适当的短持续时间，并为更长时间的数据传输安排适当更长的持续时间数组处理器的无数处理元素。在每个时钟周期内，不需要足够的时间来处理远程处理元件（3）之间的最差情况数据传输。时钟波形具有三个可识别的边缘（A，B，C），而不管其行进到各种处理元件时是否有锐度损失。三种偏移敏感活动（READ，WRITE和OPERAND SUPPLY）分别符合分配边的惯例如下：A = READ; B =操作供应 C = WRITE（读下一个）处理元件与时钟波形同步，该时钟波形针对正在执行的程序的指令进行了优化。没有时间浪费，允许在某些指令中可能发生最坏情况的数据传输，但在其他指令中不可行。

2. 发明授权

EP0392216B1 Network rearrangement method and system 失效
标题翻译：方法和系统Netzumordnung。
公开(公告)号：EP0392216B1
公开(公告)日：1995-11-29
申请号：EP90105063.3
申请日：1990-03-17
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L2012/5627

3. 发明公开

EP0379709A3 Single-fifo high speed combining switch 失效
标题翻译：单FIFO高速组合开关
公开(公告)号：EP0379709A3
公开(公告)日：1992-04-08
申请号：EP89123610.1
申请日：1989-12-21
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： G06F7/22 , G06F5/06 , G06F13/16
CPC分类号： G06F7/22 , G06F5/06 , G06F13/1631
摘要： A combining switch 10 includes a two input multiplexer 12 which receives I and J inputs from data processors and directs one of the incoming messages, if there are no contentions or congestions at a switch output port 14 and a Queue FIFO 16 is empty, directly to the output port 14 for transmission to one of a plurality of memory modules. If the output port 14 is busy and the Queue 16 is empty the incoming message is routed to the Queue FIFO 16 for storage. If the Queue FIFO 16 is not empty the incoming message is first compared by a comparator 20 to all existing messages stored in the Queue FIFO 16 to determine if the incoming message is destined for a memory address which already has a queued message. If no match is determined by comparator 20 the incoming message is routed to the Queue FIFO 16 for storage. If comparator 20 determines that the memory address and operation type of the incoming message matches that of a message already stored in the Queue FIFO 16 both the incoming message and the queued message are applied to a message combining ALU 26. The ALU 26 generates a combined message which is stored at the same Queue 16 location as the queued message which generated a comparison match with the incoming message.

4. 发明授权

EP0764905B1 An invalidation bus optimisation for multiprocessors using directory-based coherence protocols 失效
标题翻译： Ungültigkeitserklärungsbusoptimierung与基于目录的一致性协议的多处理器
公开(公告)号：EP0764905B1
公开(公告)日：2001-10-24
申请号：EP96306163.5
申请日：1996-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Baylor, Sandra Johnson , Hsu, Yarsun
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813

5. 发明公开

EP0936551A1 A hierarchical bus simple coma architecture for shared memory multiprocessors 审中-公开
标题翻译： Einfache COMA-Architektur mit hierarchyischem多媒体广播公司
公开(公告)号：EP0936551A1
公开(公告)日：1999-08-18
申请号：EP99301014.9
申请日：1999-02-11
申请人： International Business Machines Corporation
发明人： Baylor, Sandra Johnson , Hsu, Yarsun
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0831 , G06F2212/272
摘要： A method of maintaining cache coherency in a shared memory multiprocessor system having a plurality of nodes, where each node itself is a shared memory multiprocessor. With this invention, an additional shared owner state is maintained so that if a cache at the highest level of cache memory in the system issues a read or write request to a cache line that misses the highest cache level of the system, then the owner of the cache line places the cache line on the bus interconnecting the highest level of cache memories.
摘要翻译：在具有多个节点的共享存储器多处理器系统中维持高速缓存一致性的方法，其中每个节点本身是共享存储器多处理器。利用本发明，维护附加的共享所有者状态，使得如果系统中的高速缓存存储器的最高级别的高速缓存对错过系统的最高高速缓存级别的高速缓存行发出读取或写入请求，则所有者高速缓存行将高速缓存行放置在互连最高级别的高速缓冲存储器的总线上。

6. 发明授权

EP0379709B1 Single-fifo high speed combining switch 失效
标题翻译：高集交换与Einzelfifo。
公开(公告)号：EP0379709B1
公开(公告)日：1995-08-23
申请号：EP89123610.1
申请日：1989-12-21
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： G06F7/22 , G06F5/06 , G06F13/16
CPC分类号： G06F7/22 , G06F5/06 , G06F13/1631

7. 发明公开

EP0392216A3 Network rearrangement method and system 失效
标题翻译：网络安排方法与系统
公开(公告)号：EP0392216A3
公开(公告)日：1992-10-07
申请号：EP90105063.3
申请日：1990-03-17
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L2012/5627
摘要： A system (31) and method for a fault-tolerant system for parallel networks (31b) which interconnect processors and the first of the parallel networks distributed in an Omega equivalent configuration and the second of the parallel networks distributed in a reversed Omega equivalent configuration.

8. 发明公开

EP0764905A1 An invalidation bus optimisation for multiprocessors using directory-based coherence protocols 失效
标题翻译： UngültigkeitserklärungsbusoptimierungfürMultiprozessoren mit verzeichnisbasiertenKohärenzprotokollen
公开(公告)号：EP0764905A1
公开(公告)日：1997-03-26
申请号：EP96306163.5
申请日：1996-08-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Baylor, Sandra Johnson , Hsu, Yarsun
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0813
摘要： An optimization scheme for a directory-based cache coherence protocol for multistage interconnection network-based multiprocessors improves system performance by reducing network latency. The optimization scheme is scalable, targeting multiprocessor systems having a moderate number of processors. The modification of shared data is the dominant contributor to performance degradation in these systems. The directory-based cache coherence scheme uses an invalidation bus on the processor side of the network. The invalidation bus connects all the private caches in the system and processes the invalidation requests thereby eliminating the need to send invalidations across the network.
摘要翻译：用于基于多级互连网络的多处理器的基于目录的高速缓存一致性协议的优化方案通过减少网络延迟来提高系统性能。优化方案是可扩展的，针对具有中等数量处理器的多处理器系统。共享数据的修改是这些系统性能下降的主要因素。基于目录的高速缓存一致性方案在网络的处理器侧使用无效总线。无效总线连接系统中的所有私有高速缓存，并处理无效请求，从而消除了通过网络发送无效的需要。

9. 发明公开

EP0392216A2 Network rearrangement method and system 失效
标题翻译： Verfahren und SystemfürNetzumordnung。
公开(公告)号：EP0392216A2
公开(公告)日：1990-10-17
申请号：EP90105063.3
申请日：1990-03-17
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L2012/5627
摘要： A system (31) and method for a fault-tolerant system for parallel networks (31b) which interconnect processors and the first of the parallel networks distributed in an Omega equivalent configuration and the second of the parallel networks distributed in a reversed Omega equivalent configuration.
摘要翻译：一种用于并行网络（31b）的系统（31）和方法，用于并行网络（31b），其互连处理器和分布在欧米茄等效配置中的第一并行网络，并且以延迟的欧米茄等效配置分布第二并行网络。

10. 发明公开

EP0379709A2 Single-fifo high speed combining switch 失效
标题翻译： Hochgeschwindigkeits-Kombinierschalter mit Einzelfifo。
公开(公告)号：EP0379709A2
公开(公告)日：1990-08-01
申请号：EP89123610.1
申请日：1989-12-21
申请人： International Business Machines Corporation
发明人： Hsu, Yarsun
IPC分类号： G06F7/22 , G06F5/06 , G06F13/16
CPC分类号： G06F7/22 , G06F5/06 , G06F13/1631
摘要： A combining switch 10 includes a two input multiplexer 12 which receives I and J inputs from data processors and directs one of the incoming messages, if there are no contentions or congestions at a switch output port 14 and a Queue FIFO 16 is empty, directly to the output port 14 for transmission to one of a plurality of memory modules. If the output port 14 is busy and the Queue 16 is empty the incoming message is routed to the Queue FIFO 16 for storage. If the Queue FIFO 16 is not empty the incoming message is first compared by a comparator 20 to all existing messages stored in the Queue FIFO 16 to determine if the incoming message is destined for a memory address which already has a queued message. If no match is determined by comparator 20 the incoming message is routed to the Queue FIFO 16 for storage. If comparator 20 determines that the memory address and operation type of the incoming message matches that of a message already stored in the Queue FIFO 16 both the incoming message and the queued message are applied to a message combining ALU 26. The ALU 26 generates a combined message which is stored at the same Queue 16 location as the queued message which generated a comparison match with the incoming message.
摘要翻译：组合开关10包括两个输入多路复用器12，其从数据处理器接收I和J个输入并引导输入消息中的一个，如果在交换机输出端口14和队列FIFO 16为空时没有争用或拥塞，直接到输出端口14，用于传输到多个存储器模块之一。如果输出端口14正忙，并且队列16为空，则传入的消息被路由到队列FIFO 16用于存储。如果队列FIFO 16不是空的，则输入消息首先由比较器20与存储在队列FIFO 16中的所有现有消息进行比较，以确定输入消息是否发往具有排队消息的存储器地址。如果由比较器20确定不匹配，则输入消息被路由到队列FIFO 16用于存储。如果比较器20确定输入消息的存储器地址和操作类型与已经存储在队列FIFO 16中的消息的存储器地址和操作类型相匹配，则进入消息和排队消息都被应用于组合ALU26的消息。ALU 26产生组合消息被存储在与排队的消息相同的队列16位置处，其产生与传入消息的比较匹配。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式