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1. 发明授权

EP2429082B1 A compensation of loop-delay quantizer in continuous-time and hybrid sigma-delta analog-to-digital modulators 有权
标题翻译： Schleifenverzögerungskompensationsquantisierer连续时间和混合Σ-Δ模拟到数字调制器
公开(公告)号：EP2429082B1
公开(公告)日：2015-03-11
申请号：EP11392007.8
申请日：2011-06-20
申请人： Dialog Semiconductor GmbH
发明人： Loeda, Sebastian , Hague, Gary
IPC分类号： H03M3/04
CPC分类号： H03M3/37 , H03M3/452

2. 发明公开

EP2706666A1 Circuit for digitizing a sum of signals 审中-公开
标题翻译： Schallung zur Digitalisierung einer Summe von Signalen
公开(公告)号：EP2706666A1
公开(公告)日：2014-03-12
申请号：EP12183714.0
申请日：2012-09-10
申请人： IMEC , Stichting IMEC Nederland , Katholieke Universiteit Leuven
发明人： Morgado, Alonso , Porrzzo, Serena , Cannillo Francesco
IPC分类号： H03M3/04
CPC分类号： H03M3/32 , H03M3/426 , H03M3/452
摘要： The present invention relates to a circuit for digitizing a sum of at least one first input signal and a plurality of second input signals comprising
- a passive adder circuit arranged for performing a summation of the second input signals and for outputting a summation signal,
- a multi-bit quantizer circuit comprising a comparator arranged for comparing said summation signal applied at a first comparator input terminal with a signal applied at a second comparator input terminal, said signal being derived from the at least one first input signal and having an appropriate polarity so that the difference between the summation signal and said signal at the second comparator input terminal is indicative of the sum of the at least one first input signal and the plurality of second input signals, wherein the comparator is further arranged for producing a comparator output signal based on the sum of the at least one first input signal and the plurality of second input signals. The multi-bit quantizer circuit further comprises a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
摘要翻译：本发明涉及一种用于数字化至少一个第一输入信号和多个第二输入信号的和的电路，包括：被动加法器电路，被配置为执行第二输入信号的求和并输出求和信号， - 一多比特量化器电路，包括比较器，用于将在第一比较器输入端施加的所述求和信号与施加在第二比较器输入端的信号进行比较，所述信号从至少一个第一输入信号导出，并具有适当的极性第二比较器输入端的求和信号和所述信号之间的差表示至少一个第一输入信号和多个第二输入信号之和，其中该比较器进一步被布置用于产生基于比较器输出信号的比较器输出信号在所述至少一个第一输入信号和所述多个第二输入信号的和之间。多比特量化器电路还包括用于确定来自比较器输出信号的和的多位表示的控制逻辑块。

3. 发明公开

EP2421156A3 Low power high dynamic range sigma-delta modulator 审中-公开
标题翻译：具有低功耗，高动态范围的Σ-Δ调制器
公开(公告)号：EP2421156A3
公开(公告)日：2013-01-09
申请号：EP11177593.8
申请日：2011-08-15
申请人： NXP B.V.
发明人： Dijkmans, Carl , van Beldhoven, Robert H , Kup, Bernardus Martinus , Neuteboom, Harry , van der Dussen, Leon
IPC分类号： H03M3/02
CPC分类号： H03M3/434 , H03M3/452
摘要： A low power, high dynamic range sigma-delta modulator comprises a quantizer followed by a digital integrator for generating an integrated digital signal from a quantized signal. The output of the digital integrator is coupled to a digital-to-analog converter in the feedback loop of the sigma-delta modulator.

4. 发明授权

EP1813021B1 DUAL-MODE DELTA-SIGMA ANALOG TO DIGITAL CONVERTER SYSTEM AND METHOD 有权转让
标题翻译：系统和方法与双模Δ-Σ模数转换器
公开(公告)号：EP1813021B1
公开(公告)日：2013-01-09
申请号：EP05826185.0
申请日：2005-11-10
申请人： MediaTek Inc.
发明人： GEALOW, Jeffrey , FERGUSON, Jr., Paul
IPC分类号： H03M3/02
CPC分类号： H03M3/392 , H03M3/406 , H03M3/424 , H03M3/45 , H03M3/452

5. 发明公开

EP2229734A1 A MULTI-BIT SIGMA-DELTA MODULATOR WITH REDUCED NIUMBER OF BITS IN FEEDBACK PATH 有权
标题翻译：在反馈路径数量减少的位多位Σ-Δ调制器
公开(公告)号：EP2229734A1
公开(公告)日：2010-09-22
申请号：EP08862503.3
申请日：2008-12-16
申请人： ST-Ericsson SA
发明人： VAN VELDHOVEN, Robert, Henrikus, Margaretha
IPC分类号： H03M3/02 , H03M3/04
CPC分类号： H03M3/428 , H03M3/452 , H03M7/302
摘要： A sigma-delta modulator (200) for an ADC, passes an input signal to a loop filter (20), then to a multi-bit quantiser (30) of the modulator (200). An output of the quantiser (30) is passed to a digital filter (50), and a feedback signal is passed back to the loop filter (20), the feedback signal having fewer bits than are produced by the multi-bit quantiser (30). No separate feedback loop for the digital filter (50) is used, so as to reduce the need to adjust the loop filter for stable operation. The digital filter (50) can have an order greater than one in the passband of the sigma-delta modulator (200).

6. 发明公开

EP1755226A2 Delta - sigma modulators with improved noise performance 审中-公开
标题翻译： Delta-Σ调制器具有改善的噪声性能
公开(公告)号：EP1755226A2
公开(公告)日：2007-02-21
申请号：EP06125016.3
申请日：2003-04-01
申请人： Cirrus Logic, Inc.
发明人： Melanson, John Laurent , Yang, YuQing
IPC分类号： H03M3/00
CPC分类号： H03M3/368 , H03M3/424 , H03M3/452
摘要： An integrator stage for use in a delta sigma modulator includes an operational amplifier (312), an integration capacitor (CI) coupling to an output of the operational amplifier (312) and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors (+/-Cref) having first plates coupled electrically in common at a common plate node and switching circuitry (310 a-d) for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch (305 a-b) for selectively coupling the common plate node and the summing node during an integration phase.
摘要翻译：用于Δ-Σ调制器中的积分器级包括运算放大器（312），耦合到运算放大器（312）的输出端的积分电容器（CI）和运算放大器的输入端处的求和节点，以及反馈路径。反馈路径包括具有在公共板节点共同电耦合的第一板的第一和第二电容器（+/- Cref）以及用于在采样阶段期间将选定的参考电压采样到电容器的第二板上的开关电路（310a-d）。积分器级还包括用于在积分阶段期间选择性地耦合公共板节点和求和节点的开关（305a-b）。

7. 发明公开

EP0643488A1 Sigma-delta analog-to-digital converter with filtration having controlled pole-zero locations, and apparatus therefor 失效
标题翻译： Σ-Δ模拟到数字转换器与过滤器具有定义零极分布及其装置。
公开(公告)号：EP0643488A1
公开(公告)日：1995-03-15
申请号：EP94305610.1
申请日：1994-07-28
申请人： Martin Marietta Corporation
发明人： Pellon, Leopold Ernest
IPC分类号： H03M3/00
CPC分类号： H03M3/404 , H03M3/424 , H03M3/452
摘要： A sigma-delta (ΣΔ) analog-to-digital converter (ADC) (700) accepts band-limited analog signals (51), and subtracts an analog replica of an output pulse- or amplitude- density modulated (ADM) signal therefrom to produce an error signal. The error signal is processed by an analog filter or resonator (758) with a nondelayed forward path (763) and a tapped nonaccumulating delay line (775), and summed feedback (762) and feedforward (764) weights coupled to the taps, to thereby produce a resonated signal (208). An ADC (210) processes the resonated signal, and produces the ADM signal. The ADC undesirably produces quantization noise. A digital-to-analog converter (DAC) (218) noiselessly converts the PDM signal into the analog replica (206), to aid in forming the error signal. In a particular embodiment of the invention, the resonator (758) includes a recursive analog transversal filter with delays and linear weighting elements for linearity and high operating speed. The ADC (700) may be in a high-speed system such as a radar.
摘要翻译：所述Σ-Δ（〜E〜D）模拟到数字转换器（ADC）接受频带受限模拟信号，并减去到调制（ADM）信号从那里上产生错误的输出脉冲振幅或密度的类似物复制品信号。该误差信号是通过在模拟滤波器或谐振器处理与未延迟的前向路径和抽头延迟线非累积，并求和反馈以及耦合到抽头的前馈的权重，从而产生谐振信号。一个ADC处理该谐振信号，并产生ADM信号。该ADC不希望可生产量化噪声。一种数字 - 模拟转换器（DAC）PDM信号转换无声成模拟副本，在形成所述误差信号，以帮助。谐振器可以包括与延迟和线性度和高工作速度的线性加权元件的递归横向模拟滤波器。

8. 发明公开

EP0293780A2 Analog-to-digital converter employing delta-sigma modulation 失效
标题翻译：模拟数字集成器Delta-Sigmamodulation。
公开(公告)号：EP0293780A2
公开(公告)日：1988-12-07
申请号：EP88108503.9
申请日：1988-05-27
申请人： Steim, Joseph M. , Wielandt, Erhard
发明人： Steim, Joseph M. , Wielandt, Erhard
IPC分类号： H03M3/02
CPC分类号： H03M1/145 , H03M3/43 , H03M3/452 , H03M3/46
摘要： An analog-to-digital converter comprising a delta-sigma modulator (64), a multi-bit A/D converter (53), a second order differentiator (55) and an output summing element (59). The delta-sigma modulator (64) comprises two integrators (42,43), a one bit A/D converter (54), a one bit D/A converter (52) and an input summing element (41) which receives an analog input signal (40) and an output signal (48) of the one bit D/A converter (52). The output of the second integrator (43) is fed to the multi-bit A/D converter (53). The digital output (49) of the converter (53) is applied to a second order differentiator (55) where it is differentiated twice in order to digitally represent the analog output signal (57) of the input summing element (41). The second order differentiated signal (58) is digitally added to the output signal (47) of the delta-sigma modulator (64). The output (50) of the summing element (59) is a digital representation of the analog input signal (40). The analog-to-digital converter has a relatively low loop bit rate and provides a dynamic range of 120 - 140 dB.
摘要翻译：一种包括Δ-Σ调制器（64），多位A / D转换器（53），二阶微分器（55）和输出求和元件（59）的模数转换器。 Δ-Σ调制器（64）包括两个积分器（42,43），一位A / D转换器（54），一位D / A转换器（52）和输入求和元件（41），其接收模拟输入信号（40）和一位D / A转换器（52）的输出信号（48）。第二积分器（43）的输出被馈送到多位A / D转换器（53）。转换器（53）的数字输出（49）被施加到二阶微分器（55），其中它被差分两次，以便数字地表示输入求和元件（41）的模拟输出信号（57）。二阶微分信号（58）被数字地相加到Δ-Σ调制器（64）的输出信号（47）。求和元件（59）的输出（50）是模拟输入信号（40）的数字表示。模数转换器具有相对低的环路比特率，并提供120 - 140 dB的动态范围。

9. 发明公开

EP3152838A2 FEEDBACK DELAY REDUCTION IN FORCE FEEDBACK DEVICES 审中-公开
标题翻译： ÜKKOPPLUNGSVERZÖGERUNGSREDUKTIONBEIKRAFTRÜCKKOPPLUNGSVORRICHTUNGEN
公开(公告)号：EP3152838A2
公开(公告)日：2017-04-12
申请号：EP15730087.2
申请日：2015-06-08
申请人： Robert Bosch GmbH
发明人： BALACHANDRAN, Ganesh , PETKOV, Vladimir
IPC分类号： H03M3/00
CPC分类号： H04R3/00 , H03M3/37 , H03M3/406 , H03M3/422 , H03M3/452 , H03M3/454 , H04R2201/003
摘要： A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.
摘要翻译：反馈电路向换能器提供反馈信号。反馈电路包括产生反馈信号的数字表示的ADC，识别反馈的调节的数字控制器以及产生经调整的反馈信号的模拟输出的DAC。在接收到ADC的输出之前，数字控制器执行推测计算以识别来自ADC的每个输出值的反馈信号输出的调整。 ADC和DAC包括在正向通路中以零时钟周期延迟运行的Σ-Δ调制器。 ADC，数字控制器和DAC通过减小延迟来产生对反馈输出信号的调整，减少相位滞后并提高相位裕度，以保持传感器的稳定性。

10. 发明公开

EP2560285A2 Configurable continuous-time sigma-delta analog-to-digital converter 审中-公开
标题翻译： Sigma-Delta-Analog-Digital-Wandler的Konfigurierbarer zeitkontinuierlicher
公开(公告)号：EP2560285A2
公开(公告)日：2013-02-20
申请号：EP12175266.1
申请日：2012-07-06
申请人： Freescale Semiconductor, Inc.
发明人： Braswell, Brandt
IPC分类号： H03M3/04
CPC分类号： H03M3/398 , H03M3/37 , H03M3/424 , H03M3/452 , H03M3/464
摘要： An analog-to-digital converter (ADC) (10) includes a continuous time filter (14), a quantizer (18), a continuous time digital-to-analog converter (20), a discrete time DAC (24), and a switch (26). The quantizer (18) has an input terminal coupled to the output terminal of the continuous time filter (14), and a plurality of output terminals. The continuous time DAC (20) has a plurality of input terminals coupled to the plurality of output terminals of the quantizer (18), and an output terminal. The discrete time DAC (24) has a plurality of input terminals coupled to the plurality of output terminals of the quantizer (18), and an output terminal. The switch (26) has a first input terminal coupled to the output terminal of the continuous time DAC (20), a second input terminal coupled to the output terminal of the discrete time DAC (24), and an output terminal coupled to the input terminal of the continuous time filter (14).
摘要翻译：模数转换器（ADC）（10）包括连续时间滤波器（14），量化器（18），连续时间数模转换器（20），离散时间DAC（24）和开关（26）。量化器（18）具有耦合到连续时间滤波器（14）的输出端子的输入端子和多个输出端子。连续时间DAC（20）具有耦合到量化器（18）的多个输出端子的多个输入端子和输出端子。离散时间DAC（24）具有耦合到量化器（18）的多个输出端子的多个输入端子和输出端子。开关（26）具有耦合到连续时间DAC（20）的输出端的第一输入端，耦合到离散时间DAC（24）的输出端的第二输入端和耦合到输入端连续时间滤波器（14）的端子。

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