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1. 发明公开

EP0293780A2 Analog-to-digital converter employing delta-sigma modulation 失效
标题翻译：模拟数字集成器Delta-Sigmamodulation。
公开(公告)号：EP0293780A2
公开(公告)日：1988-12-07
申请号：EP88108503.9
申请日：1988-05-27
申请人： Steim, Joseph M. , Wielandt, Erhard
发明人： Steim, Joseph M. , Wielandt, Erhard
IPC分类号： H03M3/02
CPC分类号： H03M1/145 , H03M3/43 , H03M3/452 , H03M3/46
摘要： An analog-to-digital converter comprising a delta-sigma modulator (64), a multi-bit A/D converter (53), a second order differentiator (55) and an output summing element (59). The delta-sigma modulator (64) comprises two integrators (42,43), a one bit A/D converter (54), a one bit D/A converter (52) and an input summing element (41) which receives an analog input signal (40) and an output signal (48) of the one bit D/A converter (52). The output of the second integrator (43) is fed to the multi-bit A/D converter (53). The digital output (49) of the converter (53) is applied to a second order differentiator (55) where it is differentiated twice in order to digitally represent the analog output signal (57) of the input summing element (41). The second order differentiated signal (58) is digitally added to the output signal (47) of the delta-sigma modulator (64). The output (50) of the summing element (59) is a digital representation of the analog input signal (40). The analog-to-digital converter has a relatively low loop bit rate and provides a dynamic range of 120 - 140 dB.
摘要翻译：一种包括Δ-Σ调制器（64），多位A / D转换器（53），二阶微分器（55）和输出求和元件（59）的模数转换器。 Δ-Σ调制器（64）包括两个积分器（42,43），一位A / D转换器（54），一位D / A转换器（52）和输入求和元件（41），其接收模拟输入信号（40）和一位D / A转换器（52）的输出信号（48）。第二积分器（43）的输出被馈送到多位A / D转换器（53）。转换器（53）的数字输出（49）被施加到二阶微分器（55），其中它被差分两次，以便数字地表示输入求和元件（41）的模拟输出信号（57）。二阶微分信号（58）被数字地相加到Δ-Σ调制器（64）的输出信号（47）。求和元件（59）的输出（50）是模拟输入信号（40）的数字表示。模数转换器具有相对低的环路比特率，并提供120 - 140 dB的动态范围。

2. 发明授权

EP0293780B1 Analog-to-digital converter employing delta-sigma modulation 失效
标题翻译：使用DELTA-SIGMA调制的模拟数字转换器
公开(公告)号：EP0293780B1
公开(公告)日：1993-08-11
申请号：EP88108503.9
申请日：1988-05-27
申请人： Steim, Joseph M. , Wielandt, Erhard
发明人： Steim, Joseph M. , Wielandt, Erhard
IPC分类号： H03M3/02
CPC分类号： H03M1/145 , H03M3/43 , H03M3/452 , H03M3/46

3. 发明公开

EP0293780A3 Analog-to-digital converter employing delta-sigma modulation 失效
标题翻译：使用DELTA-SIGMA调制的模拟数字转换器
公开(公告)号：EP0293780A3
公开(公告)日：1990-03-21
申请号：EP88108503.9
申请日：1988-05-27
申请人： Steim, Joseph M. , Wielandt, Erhard
发明人： Steim, Joseph M. , Wielandt, Erhard
IPC分类号： H03M3/02
CPC分类号： H03M1/145 , H03M3/43 , H03M3/452 , H03M3/46
摘要： An analog-to-digital converter comprising a delta-sigma modulator (64), a multi-bit A/D converter (53), a second order differentiator (55) and an output summing element (59). The delta-sigma modulator (64) comprises two integrators (42,43), a one bit A/D converter (54), a one bit D/A converter (52) and an input summing element (41) which receives an analog input signal (40) and an output signal (48) of the one bit D/A converter (52). The output of the second integrator (43) is fed to the multi-bit A/D converter (53). The digital output (49) of the converter (53) is applied to a second order differentiator (55) where it is differentiated twice in order to digitally represent the analog output signal (57) of the input summing element (41). The second order differentiated signal (58) is digitally added to the output signal (47) of the delta-sigma modulator (64). The output (50) of the summing element (59) is a digital representation of the analog input signal (40). The analog-to-digital converter has a relatively low loop bit rate and provides a dynamic range of 120 - 140 dB.

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