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1. 发明公开

EP2683086A3 Memory efficient LDPC decoding methods and apparatus 审中-公开
标题翻译：存储器高效的LDPC解码方法和装置
公开(公告)号：EP2683086A3
公开(公告)日：2014-01-22
申请号：EP13020082.7
申请日：2005-08-01
申请人： Qualcomm Incorporated
发明人： Richardson, Tom , Novichkov, Vladimir
IPC分类号： H03M13/11
CPC分类号： H03M13/6362 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/1137
摘要： Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described. Constraining the graph to allow a particular type of partition allows the subsequent iterations to overlap in time and one can effectively reduce and/or eliminate the penalty due to the pipeline delay.

2. 发明授权

EP1407420B1 METHODS AND APPARATUS FOR DECODING LDPC CODES 有权
标题翻译：方法和装置解码LDPC码
公开(公告)号：EP1407420B1
公开(公告)日：2011-06-22
申请号：EP02739608.4
申请日：2002-05-31
申请人： QUALCOMM Incorporated
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H03M13/11
CPC分类号： H03M13/6356 , G06N3/02 , H03M13/1114 , H03M13/1131 , H03M13/1137 , H03M13/1148 , H03M13/116 , H03M13/1168 , H03M13/1177 , H03M13/6362 , H03M13/6505 , H03M13/6566
摘要： Methods and apparatus for decoding codewords (902) using message passing decoding techniques which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow decoding graph structures which are largely comprised of multiple identical copies of a much smaller graph (1000). Copies of the smaller graph are subject to a controlled permutation operation (904) to create the larger graph structure. The same controlled permutations are directly implemented to support message passing between the replicated copies of the small graph. Messages corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering messages, e.g., using a cyclic permutation operation, in each set of messages react out of a message memory so that the messages are passed to processing circuits corresponding to different copies of the small graph.

3. 发明公开

EP2270989A2 Decoding apparatus, decoding method, and program 有权
标题翻译： Dekodierungsvorrichtung，Dekodierungsverfahren und Programm
公开(公告)号：EP2270989A2
公开(公告)日：2011-01-05
申请号：EP10178005.4
申请日：2004-04-19
申请人： Sony Corporation
发明人： Yokokawa, Takashi , Miyauchi, Toshiyuki , Iida, Yasuhiro
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译：本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器存取的控制很容易，也是一个程序。 LDPC码的校验矩阵由（P×P）个单位矩阵，单位矩阵中的1至数个1被0替代的矩阵，循环移位的矩阵，矩阵，它们是两个或更多个的和，（P×P）0矩阵的和。校验节点计算器313同时执行p校验节点计算。可变节点计算器319同时执行p个可变节点计算。

4. 发明公开

EP1876716A1 DECODING APPARATUS AND DECODING METHOD 审中-公开
标题翻译： DEKODIERUNGSVORRICHTUNG UND DEKODIERUNGSVERFAHREN
公开(公告)号：EP1876716A1
公开(公告)日：2008-01-09
申请号：EP06745481.9
申请日：2006-04-20
申请人： Sony Corporation
发明人： YOKOKAWA, Takashi, c/o SONY CORPORATION , MIYAUCHI, Toshiyuki, c/o SONY CORPORATION , SHINYA, Osamu, c/o SONY CORPORATION
IPC分类号： H03M13/19
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： The present invention relates to a decoding apparatus and a decoding method, which are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section 1102 carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results D1101 supplied from a decoding intermediate result storage memory 1104 by way of a cyclic shift circuit 1101, and stores the result of the first computation process in a decoding intermediate result storage memory 1103. A computation section 415 carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results D414 supplied from a decoding intermediate result storage memory 1103 by way of a cyclic shift circuit, and stores the decoding intermediate result D415 in the decoding intermediate result storage memory 1104. The present invention can be applied to, for example, a tuner for receiving (digital) satellite broadcasts.
摘要翻译：解码装置和解码方法技术领域本发明涉及一种解码装置和解码方法，其能够在防止解码装置的电路规模增加的同时高精度地解码LDPC码。计算部1102通过利用通过循环移位电路1101从解码中间结果存储存储器1104提供的解码中间结果D1101，进行与三个校验节点处理相对应的第一计算处理，并且存储第一解码中间结果存储存储器1103中的计算处理。计算部415通过利用从解码中间结果存储存储器1103提供的解码中间结果D414通过循环的方式执行与六个可变节点处理相对应的第二计算处理并将解码中间结果D415存储在解码中间结果存储存储器1104中。本发明可以应用于例如用于接收（数字）卫星广播的调谐器。

5. 发明公开

EP2356749A2 CONTENTION-FREE PARALLEL PROCESSING MULTIMODE LDPC DECODER 审中-公开
标题翻译：无竞争并行处理多模LDPC解码器
公开(公告)号：EP2356749A2
公开(公告)日：2011-08-17
申请号：EP09832102.9
申请日：2009-12-08
申请人： Samsung Electronics Ltd.
发明人： PISEK, Eran , WANG, Yan , HENIGE, Thomas
IPC分类号： H03M13/09
CPC分类号： H04L1/0057 , H03M13/1111 , H03M13/1114 , H03M13/1122 , H03M13/1131 , H03M13/1134 , H03M13/1137 , H03M13/114 , H03M13/1165 , H03M13/1188 , H03M13/616 , H03M13/6516 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/6544 , H03M13/6561 , H03M13/6569 , H04L1/005 , H04L1/0052
摘要： A receiver capable of decoding encoded transmissions. The receiver includes a number of receive antennas for receiving data; a plurality of memory units for storing the received data; and a number of decoders configured to perform a Low Density Parity Check (LDPC) decoding operation. Each of the decoders further is configured to independently decode at least a portion of the received data using a portion of a decoding matrix. Each of the number of decoders coordinates the low density parity check decoding operation with other decoders. The decoders can use a parallel process, a pipeline process or a combination of a parallel and pipeline process.

6. 发明公开

EP2270990A3 Decoding apparatus, decoding method, and program 有权
标题翻译：解码装置，解码方法和程序
公开(公告)号：EP2270990A3
公开(公告)日：2011-06-22
申请号：EP10178046.8
申请日：2004-04-19
申请人： Sony Corporation
发明人： Yokokawa, Takashi , Miyauchi, Toshiyuki , Iida, Yasuhiro
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculation.

7. 发明公开

EP2171857A1 SHUFFLED LDPC DECODING 审中-公开
标题翻译： SHUFFLED LDPC解码
公开(公告)号：EP2171857A1
公开(公告)日：2010-04-07
申请号：EP08763425.9
申请日：2008-07-01
申请人： NXP B.V.
发明人： DIELISSEN, John
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1165 , H03M13/6527 , H03M13/6544 , H03M13/6566 , H03M13/658 , H03M13/6583 , H03M13/6588
摘要： An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages λϰm from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages Λmn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing means. The principle of 'staggered' or 'shuffled' LDPC decoding is used. One embodiment is designed for multi-diagonal circulants.
摘要翻译： LDPC解码器基于对数似然比置信传播算法迭代解码由包括多个循环的奇偶校验矩阵H表示的LDPC码。第一计算装置（1010）根据存储在第一存储器1005中的对应符号值的表示和来自先前迭代的校验节点消息Δmn来计算下一个迭代符号消息λk。混洗器（1030）根据相应子矩阵中的非零元素的位置来改变从第一计算装置（1010）接收到的符号消息的序列。第二计算装置（DP-O，DP-1，DP-D-I）根据从桶形移位器接收的符号消息计算校验节点消息，并将计算的校验节点消息的表示存储在第二存储器（1015）中。第三计算装置（1020）根据第一和第二计算装置的输出更新第一存储器中符号值的表示。使用'交错'或'混洗'LDPC解码的原理。一个实施例被设计用于多对角线循环。

8. 发明公开

EP1876716A4 DECODING APPARATUS AND DECODING METHOD 审中-公开
标题翻译： DEKODIERUNGSVORRICHTUNG UND DEKODIERUNGSVERFAHREN
公开(公告)号：EP1876716A4
公开(公告)日：2008-07-23
申请号：EP06745481
申请日：2006-04-20
申请人： SONY CORP
发明人： YOKOKAWA TAKASHI , MIYAUCHI TOSHIYUKI , SHINYA OSAMU
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1137 , H03M13/116 , H03M13/6505 , H03M13/6566
摘要： A decoding apparatus and a decoding method wherein the decoding of LDPC codes can be accurately performed, while the apparatus scale can be suppressed. A calculating part (1102) uses a decoding in-progress result (D1101) received from a decoding in-progress result storage memory (1104) via a cyclic shift circuit (1101) to perform a first computation corresponding to three check node computations, and causes a decoding in-progress result storage memory (1103) to store a decoding in-progress result (D1102) from the first computation. A calculating part (415) uses a decoding in-progress result (D414) received from the decoding in-progress result storage memory (1103) via the cyclic shift circuit to perform a second computation corresponding to six variable node computations, and causes a decoding in-progress result storage memory (1104) to store a decoding in-progress result (D415) from the second computation. This invention can be applied to, for example, a turner for receiving satellite broadcasts.
摘要翻译：一种解码设备和解码方法，其中可以准确地执行LDPC码的解码，同时可以抑制设备规模。计算部（1102）使用经由循环移位电路（1101）从解码中进行结果保存存储器（1104）接收到的解码进行中结果（D1101），进行与3个校验节点运算对应的第1运算，使解码进行中结果存储器（1103）存储来自第一计算的解码进行中结果（D1102）。运算部（415）使用经由循环移位电路从解码进行中结果保存存储器（1103）接收到的解码进行中结果（D414），进行与6个变量节点运算对应的第二运算，并进行解码正在进行结果存储器（1104）存储来自第二计算的解码进行中结果（D415）。本发明可以应用于例如用于接收卫星广播的调谐器。

9. 发明公开

EP1782541A2 MEMORY EFFICIENT LDPC DECODING METHODS AND APPARATUS 审中-公开
标题翻译：内存使用效率，LDPC解码方法和装置
公开(公告)号：EP1782541A2
公开(公告)日：2007-05-09
申请号：EP05782140.7
申请日：2005-08-01
申请人： Flarion Technologies, INC.
发明人： RICHARDSON, Tom , NOVICHKOV, Vladimir
IPC分类号： H03M13/00
CPC分类号： H03M13/6362 , H03M13/1105 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1122 , H03M13/1137
摘要： Methods and apparatus for implementing memory efficient LDPC decodes are described. In accordance with the invention message information is stored in a compressed state for check node processing operations. The state for a check node is fully updated and then subject to an extraction process to generate check node to variable node messages. The signs of messages received from variable nodes may be stored by the check node processor module of the invention for use in message extraction. The check node processor can process messages in variable node order thereby allowing the variable node processor and check node processor to operate on messages in the same order reducing or eliminating the need to buffer and/or reorder messages passed between check nodes and variable nodes. Graph structures which allow check node processing on one graph iteration to proceed before the previous graph iteration has been completed are also described.

10. 发明公开

EP1673870A1 METHOD FOR ENCODING LOW-DENSITY PARITY CHECK CODE 有权
标题翻译：方法编码LDPC码
公开(公告)号：EP1673870A1
公开(公告)日：2006-06-28
申请号：EP04793492.2
申请日：2004-10-14
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： YU, Nam-Yul, 812-804 Byeokjeokgol 8-danji APT. , KIM, M., 102-902 Yaehyunmaeul Hyundaihometown
IPC分类号： H03M13/11
CPC分类号： H03M13/1197 , H03M13/1114 , H03M13/1137 , H03M13/1162 , H03M13/118 , H03M13/1185 , H03M13/611
摘要： An apparatus and method for encoding low-density parity check (LDPC) codes. The method for generating a low-density parity check code formed of an information-part matrix and a parity-part matrix comprises the steps of converting the information-part matrix into an array code structure and assigning a degree sequence to each submatrix column; extending a dual-diagonal matrix corresponding to the party-part matrix such that an offset value between diagonals has a random value; lifting the normalized dual-diagonal matrix; determining an offset value for cyclic column shift for each submatrix of the lifted normalized dual-diagonal matrix; and determining a parity symbol corresponding to a column of the parity-part matrix.

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