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1. 发明授权

EP2157753B1 Control of interpolation for channel estimation 有权
标题翻译： Interpolationsreglung用于信道估计
公开(公告)号：EP2157753B1
公开(公告)日：2011-11-23
申请号：EP09251761.4
申请日：2009-07-08
申请人： Sony Corporation
发明人： Kawauchi, Hidetoshi , Goto, Yuken , Okamoto, Takuya , Miyauchi, Toshiyuki
IPC分类号： H04L25/02 , H04L27/26 , H04L25/03 , H04L5/00
CPC分类号： H04L25/0234 , H04L5/0007 , H04L5/0048 , H04L25/0216 , H04L25/022 , H04L25/03159 , H04L27/2605 , H04L27/2647 , H04L27/2657 , H04L27/2662 , H04L2025/03414

2. 发明公开

EP2270990A3 Decoding apparatus, decoding method, and program 有权
标题翻译：解码装置，解码方法和程序
公开(公告)号：EP2270990A3
公开(公告)日：2011-06-22
申请号：EP10178046.8
申请日：2004-04-19
申请人： Sony Corporation
发明人： Yokokawa, Takashi , Miyauchi, Toshiyuki , Iida, Yasuhiro
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculation.

3. 发明公开

EP2157753A2 Control of interpolation for channel estimation 有权
标题翻译：国际刑警
公开(公告)号：EP2157753A2
公开(公告)日：2010-02-24
申请号：EP09251761.4
申请日：2009-07-08
申请人： Sony Corporation
发明人： Kawauchi, Hidetoshi , Goto, Yuken , Okamoto, Takuya , Miyauchi, Toshiyuki
IPC分类号： H04L25/02
CPC分类号： H04L25/0234 , H04L5/0007 , H04L5/0048 , H04L25/0216 , H04L25/022 , H04L25/03159 , H04L27/2605 , H04L27/2647 , H04L27/2657 , H04L27/2662 , H04L2025/03414
摘要： A receiving device extracts pilots signals from a received signal (201) and estimates the characteristics of the transmission line (204). The estimates are interpolated in the time and frequency domains (321,322). The bandwidths of the interpolators are adaptively controlled (335).
摘要翻译：接收装置从接收信号（201）中提取导频信号并估计传输线（204）的特性。估计值在时域和频域内插（321,322）。插值器的带宽被自适应地控制（335）。

4. 发明公开

EP0924863A3 Viterbi decoding apparatus and viterbi decoding method 审中-公开
标题翻译：维特比译码系统和程序
公开(公告)号：EP0924863A3
公开(公告)日：2004-06-09
申请号：EP98124034.4
申请日：1998-12-17
申请人： SONY CORPORATION
发明人： Hattori, Masayuki , Miyauchi, Toshiyuki
IPC分类号： H03M13/00
CPC分类号： H03M13/6583 , H03M13/4107 , H03M13/4123 , H03M13/4161 , H03M13/4176
摘要： A register train is provided in addition to a train of memory cells as many as a cut length which are arranged in correspondence to each state. Outputs of selectors at respective stages in the register train corresponding to state 00 are inputted to a register 1021 in the register train and selectors. Outputs of the registers at the front stages are inputted to those three selectors, respectively. The three selectors switch outputs to the post stages in accordance with a control by a control circuit when a reception word is terminated and in the other cases. Thus, when the reception word is terminated, information stored in the register train is transferred as it is. By such an operation, a path which reaches state 00 can be decoded when a reception word is terminated.

5. 发明公开

EP1071217A1 DECODER AND DECODING METHOD 审中-公开
标题翻译： DEKODIERUNGSVERFAHREN DEKODER
公开(公告)号：EP1071217A1
公开(公告)日：2001-01-24
申请号：EP99959802.2
申请日：1999-12-14
申请人： Sony Corporation
发明人： Ikeda, Tamotsu , Miyauchi, Toshiyuki
IPC分类号： H03M1/00
CPC分类号： H03M1/00 , H03M13/23 , H03M13/41 , H04B7/185 , H04L27/00 , H04L27/22
摘要： The deterioration of an error characteristic obtained at a point where a transfer method is changed is suppressed. A first adder calculates a SM value obtained when the state 00 is changed to the state 00, and outputs it to a comparator. A second adder calculates a SM value obtained when the state 01 is changed to the state 00, and outputs it to the comparator. The comparator compares the SM values, selects a path having the larger likelihood, and outputs to a register having a set and a reset. An ACS controller detects a condition in which the state transition of fixed information TAB1 is uniquely determined, and outputs a reset signal to the register having a set and a reset, which stores the SM value of that state, to set the value of the register to zero. The ACS controller 85 also outputs set signals to registers having sets and resets, which store the SM values of the states other than the state 00 of the fixed information TAB1, to set them to the maximum value.
摘要翻译：在转印方法改变的点处获得的误差特性的劣化被抑制。第一加法器计算当状态00变为状态00时获得的SM值，并将其输出到比较器。第二加法器计算当状态01改变为状态00时获得的SM值，并将其输出到比较器。比较器比较SM值，选择具有较大似然性的路径，并输出到具有置位和复位的寄存器。 ACS控制器检测固定信息TAB1的状态转移被唯一确定的条件，并将复位信号输出到存储有该状态的SM值的集合和复位寄存器，以设置寄存器的值到零。 ACS控制器85还将设置信号输出到具有集合和复位的寄存器，该寄存器存储除了固定信息TAB1的状态00之外的状态的SM值，以将它们设置为最大值。

6. 发明公开

EP1739843A3 Viterbi decoding 有权
标题翻译：维特比译码
公开(公告)号：EP1739843A3
公开(公告)日：2011-12-07
申请号：EP06253258.5
申请日：2006-06-23
申请人： Sony Corporation
发明人： Miyauchi, Toshiyuki , Mizutani, Yuichi
IPC分类号： H03M13/41
CPC分类号： H03M13/4176 , H03M13/4169 , H03M13/6502
摘要： The present invention can reduce power consumption at the time of tracing. The present invention provides a viterbi decoding apparatus for decoding convolution codes, which includes a path memory unit that stores one of two paths toward respective transition states of a convolution code, as a selected path, for a plurality of continuous time points, a tracing unit that traces a selected path stored in the path memory unit in a reversed-time direction, thereby decoding a convolution code at respective time points, each of the time points being prior to a predetermined trace-skipping period, and a control unit that controls the path memory unit, wherein the path memory unit has a storage area designed to store selected paths assuming respective transition states at respective time points, the storage area is divided into sub-areas from the lowest order of transition state, each of the sub-areas corresponding to predetermined number of bits, and reading data can be stopped for each sub-area, and the control unit designates sub-areas from which no selected path needs to be read at respective time points so as to stop reading data from the designated sub-areas.

7. 发明公开

EP2270989A2 Decoding apparatus, decoding method, and program 有权
标题翻译： Dekodierungsvorrichtung，Dekodierungsverfahren und Programm
公开(公告)号：EP2270989A2
公开(公告)日：2011-01-05
申请号：EP10178005.4
申请日：2004-04-19
申请人： Sony Corporation
发明人： Yokokawa, Takashi , Miyauchi, Toshiyuki , Iida, Yasuhiro
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/11 , H03M13/1114 , H03M13/1134 , H03M13/1137 , H03M13/1145 , H03M13/1188 , H03M13/6505 , H03M13/6566 , H03M13/6577
摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P × P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P × P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.
摘要翻译：本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器存取的控制很容易，也是一个程序。 LDPC码的校验矩阵由（P×P）个单位矩阵，单位矩阵中的1至数个1被0替代的矩阵，循环移位的矩阵，矩阵，它们是两个或更多个的和，（P×P）0矩阵的和。校验节点计算器313同时执行p校验节点计算。可变节点计算器319同时执行p个可变节点计算。

8. 发明公开

EP2169893A2 Determination of a starting point of the FFT window in an OFDM receiver 有权
标题翻译： Bestimmung eine Anfangspunktes des FFT Fensters in einem OFDMEmpfänger
公开(公告)号：EP2169893A2
公开(公告)日：2010-03-31
申请号：EP09252278.8
申请日：2009-09-25
申请人： Sony Corporation
发明人： Kawauchi, Hidetoshi c/oSony Coriporation , Hattori, Masayuki c/o Sony Corportion , Yokokawa, Takashi c/o Sony Corportation , Shimizu, Kazuhiro c/o Sony Corportion , Funamoto,Kazuhisa c/o Sony Corporation , Miyauchi, Toshiyuki
IPC分类号： H04L27/26
CPC分类号： H04L27/2662 , H04L25/0232 , H04L25/03159 , H04L27/2656 , H04L27/2665
摘要： A receiving apparatus includes: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section is configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.
摘要翻译：接收装置包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的目标信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; 并且FFT部被配置为通过将由选择部选择的开始位置与FFT时域信号进行FFT作为FFT间隔的开始位置，以便生成第一OFDM频域信号。

9. 发明公开

EP1143440A3 Method and apparatus for reproducing data and method and apparatus for recording and/or reproducing data 审中-公开
标题翻译：用于记录和/或再现数据的方法和用于数据再现装置，以及方法和装置
公开(公告)号：EP1143440A3
公开(公告)日：2005-01-05
申请号：EP01302599.4
申请日：2001-03-21
申请人： SONY CORPORATION
发明人： Hattori, Masayuki , Murayama, Jun , Miyauchi, Toshiyuki
IPC分类号： G11B20/10 , G11B20/18 , G11B20/14 , H03M13/29 , H03M13/45 , H03M5/14
CPC分类号： H03M13/6325 , G11B20/10009 , G11B20/1426 , G11B20/1866 , G11B2020/1434 , G11B2020/1446 , H03M5/14 , H03M13/27 , H03M13/2957 , H03M13/2972 , H03M13/45 , H03M13/6343
摘要： A method and apparatus for recording or reproducing data in which high performance encoding and a high efficiency decoding are realized to lower the decoding error rate. A magnetic recording and/or reproducing apparatus 50 includes, in a recording system, a modulation encoder 52 for modulation encoding input data in a predetermined fashion and an interleaver 53 for interleaving data supplied from the modulation encoder 52 to re-array the data sequence. The magnetic recording and/or reproducing apparatus 50 also includes, in a reproducing system, a first deinterleaver for interleaving the input data for re-arraying the data sequence so that the bit sequence of data re-arrayed by the interleaver 53 will be restored to its original bit sequence, a modulation soft input soft output (SISO) decoder for modulation decoding data supplied from the first deinterleaver and a second deinterleaver for interleaving data corresponding to a difference value between data output by the modulation SISO decoder and data output by the first deinterleaver to re-array the data sequence of the difference data.

10. 发明公开

EP1137002A1 Method and apparatus for recording and reproducing, using concatenated encoding and iterative decoding 审中-公开
标题翻译：方法和装置，用于记录和再现数据，使用级联编码和迭代译码的下
公开(公告)号：EP1137002A1
公开(公告)日：2001-09-26
申请号：EP01302600.0
申请日：2001-03-21
申请人： SONY CORPORATION
发明人： Miyauchi, Toshiyuki , Hattori, Masayuki , Murayama, Jun
IPC分类号： G11B20/10 , H03M13/39
CPC分类号： G11B20/10 , H03M13/39
摘要： A magnetic recording and/or reproducing apparatus in which the decoding error rate is to be lowered through realization of the high-performance encoding and the high efficiently decoding. To this end, a magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction encoding input data, an interleaver 52 for interleaving data supplied from the error correction coder 51 for re-arraying the data sequence, a modulation encoder 53 for modulation encoding the data from the interleaver 52 in a predetermined fashion and an interleaver 54 for interleaving the data from the modulation encoder 53 for re-arraying the data sequence. The magnetic recording and/or reproducing apparatus 50 also includes, in its reproduction system, a channel, modulation and error correction turbo decoder 64 formed by concatenation of an error correction soft decoder and a modulation decoder for decoding the input data with the interposition of two deinterleavers and two interleavers.
摘要翻译：一种磁记录和/或再现装置，其中所述解码错误率是通过高性能编码的实现和有效地高解码降低。为此，磁记录和/或再现装置50包括，在其记录系统中，一个错误校正编码器51，用于纠错编码的输入数据到交织器52，用于从纠错编码器提供51重新排列交错数据数据序列，用于调制从交织器52以预定的方式进行编码的数据，并到交织器54，用于从调制编码器53交织的数据重新排列的数据序列的调制编码器53。磁记录和/或再现装置50因此包括在其再现系统中，一个信道，调制和纠错turbo解码器64由一个误差校正软解码器的级联以及用于将输入数据与两个插置进行解码的调制解码器FORMED 解交织器和两个交织。

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