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1. 发明公开

EP1889412A2 ELECTRONIC DEVICE AND METHOD OF COMMUNICATION RESOURCE ALLOCATION 有权
标题翻译：电子设备和方法通信资源分配
公开(公告)号：EP1889412A2
公开(公告)日：2008-02-20
申请号：EP06744916.5
申请日：2006-05-11
申请人： NXP B.V.
发明人： RIJPKEMA, Edwin , DIELISSEN, John
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L45/00 , H04Q2213/13098 , H04Q2213/1332 , H04Q2213/13322
摘要： An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IPl - IP5) to enable a communication between the processing modules (IPl - IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IPl - IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (TO - T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (TO - T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (TO - T4).

2. 发明公开

EP2171857A1 SHUFFLED LDPC DECODING 审中-公开
标题翻译： SHUFFLED LDPC解码
公开(公告)号：EP2171857A1
公开(公告)日：2010-04-07
申请号：EP08763425.9
申请日：2008-07-01
申请人： NXP B.V.
发明人： DIELISSEN, John
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/1114 , H03M13/1117 , H03M13/112 , H03M13/1122 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1165 , H03M13/6527 , H03M13/6544 , H03M13/6566 , H03M13/658 , H03M13/6583 , H03M13/6588
摘要： An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means (1010) compute for a next iteration symbol messages λϰm from a representation of a corresponding symbol value stored in a first memory 1005 and from check node messages Λmn from a previous iteration. A shuffler (1030) changes a sequence of the symbol message received from the first computation means (1010) in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (1015). Third computation means (1020) update the representation of the symbol values in the first memory in dependence on output of the first and second computing means. The principle of 'staggered' or 'shuffled' LDPC decoding is used. One embodiment is designed for multi-diagonal circulants.
摘要翻译： LDPC解码器基于对数似然比置信传播算法迭代解码由包括多个循环的奇偶校验矩阵H表示的LDPC码。第一计算装置（1010）根据存储在第一存储器1005中的对应符号值的表示和来自先前迭代的校验节点消息Δmn来计算下一个迭代符号消息λk。混洗器（1030）根据相应子矩阵中的非零元素的位置来改变从第一计算装置（1010）接收到的符号消息的序列。第二计算装置（DP-O，DP-1，DP-D-I）根据从桶形移位器接收的符号消息计算校验节点消息，并将计算的校验节点消息的表示存储在第二存储器（1015）中。第三计算装置（1020）根据第一和第二计算装置的输出更新第一存储器中符号值的表示。使用'交错'或'混洗'LDPC解码的原理。一个实施例被设计用于多对角线循环。

3. 发明授权

EP1889419B1 INTEGRATED CIRCUIT WITH INTERNAL COMMUNICATION NETWORK 有权
标题翻译： INTEGRIERTE SCHALTUNG MIT INTERNEM KOMMUNIKATIONSNETZ
公开(公告)号：EP1889419B1
公开(公告)日：2009-07-22
申请号：EP06765683.5
申请日：2006-05-17
申请人： NXP B.V.
发明人： RIJPKEMA, Edwin , DIELISSEN, John
IPC分类号： H04L12/56
CPC分类号： H04L47/801 , H04L45/00 , H04L45/24 , H04L45/38 , H04L45/60 , H04L47/122 , H04L47/125 , H04L47/15 , H04L47/24 , H04L47/2441 , H04L47/70 , H04L47/765 , H04L47/829
摘要： An integrated circuit comprises a plurality of data processing circuits (10) and a communication network (12) coupled between the data processing circuits (10). The communication network (12) comprises connections (122) and router circuits (120) coupled between the connections (122). Memory is provided to store definitions for respective data streams, of respective paths along the connections (122), for controlling the router circuits (120) to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams. The combination of the new paths and the future paths is taken from selectable combinations that include at least one combination wherein an initial path for at least one of the original data streams has been rerouted with respect to the initial path. The initial path for the at least one of the original data streams is reprogrammed if the path for that original data stream is rerouted in the selected combination, without interrupting transmission of data items of data streams other than the at least one of the original data streams. Subsequently transmission of data items is started along the new path.
摘要翻译：集成电路包括耦合在数据处理电路（10）之间的多个数据处理电路（10）和通信网络（12）。通信网络（12）包括耦合在连接（122）之间的连接（122）和路由器电路（120）。提供存储器以存储沿着连接（122）的各个路径的相应数据流的定义，用于控制路由器电路（120）沿着针对该相应数据流编程的相应路径的每个相应数据流传输每个数据项。最初定义并启动一组原始数据流的初始路径。随后可以添加额外的数据流。如果是，则将新路径与原始数据流的未来路径结合选择。新路径和未来路径的组合取自包括至少一个组合的可选组合，其中至少一个原始数据流的初始路径相对于初始路径被重新路由。如果原始数据流的路径以所选择的组合重新路由，则重新编程原始数据流中的至少一个原始数据流的初始路径，而不会中断除了至少一个原始数据流之外的数据流的数据项的传输。随后，沿新路径开始传输数据项。

4. 发明公开

EP1889419A2 INTEGRATED CIRCUIT WITH INTERNAL COMMUNICATION NETWORK 有权
标题翻译：具有内部通信网络集成电路
公开(公告)号：EP1889419A2
公开(公告)日：2008-02-20
申请号：EP06765683.5
申请日：2006-05-17
申请人： NXP B.V.
发明人： RIJPKEMA, Edwin , DIELISSEN, John
IPC分类号： H04L12/56
CPC分类号： H04L47/801 , H04L45/00 , H04L45/24 , H04L45/38 , H04L45/60 , H04L47/122 , H04L47/125 , H04L47/15 , H04L47/24 , H04L47/2441 , H04L47/70 , H04L47/765 , H04L47/829
摘要： An integrated circuit comprises a plurality of data processing circuits (10) and a communication network (12) coupled between the data processing circuits (10). The communication network (12) comprises connections (122) and router circuits (120) coupled between the connections (122). Memory is provided to store definitions for respective data streams, of respective paths along the connections (122), for controlling the router circuits (120) to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams. The combination of the new paths and the future paths is taken from selectable combinations that include at least one combination wherein an initial path for at least one of the original data streams has been rerouted with respect to the initial path. The initial path for the at least one of the original data streams is reprogrammed if the path for that original data stream is rerouted in the selected combination, without interrupting transmission of data items of data streams other than the at least one of the original data streams. Subsequently transmission of data items is started along the new path.

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