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1. 发明公开

EP3289590A2 FULLY VALID-GATED READ AND WRITE FOR LOW POWER ARRAY 有权转让
标题翻译：完全有效的读取和写入低功率阵列
公开(公告)号：EP3289590A2
公开(公告)日：2018-03-07
申请号：EP16716107.4
申请日：2016-03-28
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , MARTZLOFF, Jason Philip , SWEITZER, Robert Andrew
IPC分类号： G11C7/12 , G11C8/08 , G11C11/419 , G11C7/10
CPC分类号： G11C7/106 , G11C7/10 , G11C7/1009 , G11C7/1066 , G11C7/1087 , G11C7/109 , G11C7/1093 , G11C7/12 , G11C7/22 , G11C8/08 , G11C11/419
摘要： In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

2. 发明授权

EP3289590B1 FULLY VALID-GATED READ FOR LOW POWER MEMORY ARRAY 有权转让
公开(公告)号：EP3289590B1
公开(公告)日：2019-11-27
申请号：EP16716107.4
申请日：2016-03-28
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , MARTZLOFF, Jason Philip , SWEITZER, Robert Andrew
IPC分类号： G11C7/12 , G11C8/08 , G11C11/419 , G11C7/10

3. 发明公开

EP2087513A2 CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：内容可寻址存储器
公开(公告)号：EP2087513A2
公开(公告)日：2009-08-12
申请号：EP07864615.5
申请日：2007-11-19
申请人： QUALCOMM Incorporated
发明人： CHAI, Chiaming , HOFF, David Paul , MARTZLOFF, Jason Philip , PHAN, Michael Thaithanh , VARMA, Manju Rathna
IPC分类号： H01L21/8239 , H01L27/02 , H01L27/105 , G11C15/04
CPC分类号： H01L27/105 , G11C11/412 , G11C15/00 , G11C15/04 , H01L21/8221 , H01L27/0207 , H01L27/0688 , H01L27/1052
摘要： A content addressable memory (CAM) is disclosed. The CAM has first and second CAM cells in which each adjacent CAM cell is rotated 180° relative to its neighbor, which provides a compact physical arrangement having overall matched CAM array cell and RAM array cell row heights. Further, an interleaved set scheme can be applied to the CAM cells to provide reduced routing of compare signals and reduced parasitic capacitance.

4. 发明授权

EP2954405B1 HYBRID DYNAMIC-STATIC ENCODER WITH HIT AND MULTI-HIT DETECTION 有权
标题翻译：具有HIT和多点检测的混合动态静态编码器
公开(公告)号：EP2954405B1
公开(公告)日：2017-05-31
申请号：EP14706732.6
申请日：2014-02-06
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , DELLA ROVA, Tracey A. , MARTZLOFF, Jason P.
IPC分类号： G06F7/74 , G11C15/04 , H03K19/00
CPC分类号： G11C15/04 , G06F7/74 , G11C15/043 , H03K19/0013

5. 发明授权

EP2891153B1 DUMMY READ TO PREVENT CROWBAR CURRENT DURING READ-WRITE COLLISIONS IN MEMORY ARRAYS WITH CROSSCOUPLED BITLINE KEEPERS 有权
标题翻译： DUMMY阅读预防浪涌电流在读/写冲突存储器阵列中具有交叉耦合位线上饲养员
公开(公告)号：EP2891153B1
公开(公告)日：2016-09-28
申请号：EP13795029.1
申请日：2013-10-29
申请人： Qualcomm Incorporated
发明人： SHANKAR, Harish , HOFF, David Paul , GARG, Manish
IPC分类号： G11C8/16 , G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/412 , G11C5/063 , G11C8/08 , G11C8/16 , G11C11/413 , G11C11/418

6. 发明公开

EP2954405A1 HYBRID DYNAMIC-STATIC ENCODER WITH HIT AND MULTI-HIT DETECTION 有权
标题翻译：混合动态/静态CODER的检测的“里找到”和“a数量”
公开(公告)号：EP2954405A1
公开(公告)日：2015-12-16
申请号：EP14706732.6
申请日：2014-02-06
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , DELLA ROVA, Tracey A. , MARTZLOFF, Jason P.
IPC分类号： G06F7/74 , G11C15/04 , H03K19/00
CPC分类号： G11C15/04 , G06F7/74 , G11C15/043 , H03K19/0013
摘要： The hybrid dynamic-static encoder described herein combines dynamic and static logic to provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder includes identical top and bottom halves, which are combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half uses a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith are evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder has a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.
摘要翻译：描述的混合动态静态编码器可以结合动态和静态结构和逻辑上的设计特征也策略性地划分动态网和逻辑，以基本上消除冗余，并由此在等效逻辑延迟与提供相对于一个完全动态的编码器面积，功率和泄漏储蓄，例如，混合动态静态编码器可包括相同的上半部和下半部，其可以被组合以产生最终的编码索引，命中，和多命中输出。帮助可以使用动态网与各行的索引位每个编码器做点缀相匹配的搜索关键字。如果某行已星罗棋布，表示DASS模具行相匹配的搜索键，与有可能进行评估，以反映与该行相关的指数相关联的动态网。因此，混合动态静态编码器可具有一组减少的更小的动态网做杠杆冗余下拉结构横跨索引，命中，并击中多动态网。

7. 发明公开

EP2761621A1 METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL 有权
标题翻译：方法和装置与多个端子的SRAM存储单元减少渗漏
公开(公告)号：EP2761621A1
公开(公告)日：2014-08-06
申请号：EP12777992.4
申请日：2012-09-30
申请人： Qualcomm Incorporated
发明人： PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
IPC分类号： G11C11/413
CPC分类号： G11C11/413 , G11C5/148
摘要： Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

8. 发明公开

EP3198609A1 VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE 有权
标题翻译：电压电平移位自锁定写辅助
公开(公告)号：EP3198609A1
公开(公告)日：2017-08-02
申请号：EP15770996.5
申请日：2015-09-09
申请人： Qualcomm Incorporated
发明人： HOFF, David Paul , KULKARNI, Amey , MARTZLOFF, Jason Philip , LILES, Stephen Edward
IPC分类号： G11C11/419 , G11C7/12 , G11C5/14 , G11C7/10 , H03K19/017
CPC分类号： G11C7/12 , G11C5/14 , G11C7/1084 , G11C7/1093 , G11C7/1096 , G11C11/419 , H03K3/356104 , H03K3/35613 , H03K3/356139 , H03K3/356165 , H03K3/356173
摘要： Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.
摘要翻译：用于产生电压电平移动的自时钟写入辅助的系统和方法包括在第一电压域中具有自时钟的真和补数据输入信号的电路。第一和第二全电压电平移位器被配置为基于第一电压域中的自时钟的真和补数据输入信号在第二电压域中产生电压电平移位的自时钟中间真和补数信号。包括第一互补金属氧化物半导体（CMOS）电路和第二互补金属氧化物半导体（CMOS）电路的三态逻辑被配置为基于电压电平产生用于为第二电压域中的存储器阵列提供写入辅助的电压电平偏移的自时钟三态真和互补输出信号移动自时钟中间真实和补充信号。

9. 发明公开

EP2756501A1 ADAPTIVE READ WORDLINE VOLTAGE BOOSTING APPARATUS AND METHOD FOR MULTI-PORT SRAM 审中-公开
标题翻译：一种多端口SRAM自适应读字线升压和方法
公开(公告)号：EP2756501A1
公开(公告)日：2014-07-23
申请号：EP12766529.7
申请日：2012-09-12
申请人： Qualcomm Incorporated
发明人： GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
IPC分类号： G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/418
摘要： Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.

10. 发明授权

EP2087513B1 CONTENT ADDRESSABLE MEMORY 有权
公开(公告)号：EP2087513B1
公开(公告)日：2019-07-10
申请号：EP07864615.5
申请日：2007-11-19
申请人： QUALCOMM Incorporated
发明人： CHAI, Chiaming , HOFF, David Paul , MARTZLOFF, Jason Philip , PHAN, Michael Thaithanh , VARMA, Manju Rathna
IPC分类号： H01L21/8239 , H01L27/02 , H01L27/105 , G11C15/04 , G11C11/412 , H01L21/822 , H01L27/06

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