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1. 发明公开

EP1469604A4 TWO-MODULUS PRESCALER CIRCUIT 有权
标题翻译：模量ZWEI-VORSKALIERERSCHALTUNG
公开(公告)号：EP1469604A4
公开(公告)日：2005-02-02
申请号：EP02786127
申请日：2002-12-17
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONICS CORP
发明人： YAMAGISHI AKIHIRO , TSUKAHARA TSUNEO , SHIMPO YUKIO
IPC分类号： H03K21/00 , H03K23/64 , H03K23/66
CPC分类号： H03K23/667
摘要： A prescaler circuit comprising n DFF circuits (n>=3); a first multi-input logic gate circuit having two or more inputs; and a second multi-input logic gate circuit, wherein the output terminals of the first multi-input logic gate circuit are connected to the data input terminals of a first DFF circuit; the output terminals of the first through (n - 2)-th DFF circuits are connected to the data input terminals of the second through (n - 1)-th DFF circuits, respectively; the output terminals of the (n - 1)-th and n-th DFF circuits are connected to the input terminals of the first multi-input logic gate circuit; switch signals and the output signals of the (n - 1)-th DFF circuit are inputted to the second multi-input logic gate circuit; the output terminals of the second multi-input logic gate circuit are connected to the data input terminals of the n-th DFF circuit; and wherein all of the foregoing connections use differential signals.
摘要翻译：包含n个DFF电路（n> = 3）的预分频器电路; 具有两个或更多个输入的第一多输入逻辑门电路; 以及第二多输入逻辑门电路，其中第一多输入逻辑门电路的输出端连接到第一DFF电路的数据输入端; 第一到第（n-2）DFF电路的输出端分别连接到第二到第（n-1）DFF电路的数据输入端; 第（n-1）和第n个DFF电路的输出端连接到第一多输入逻辑门电路的输入端; 开关信号和第（n-1）DFF电路的输出信号被输入到第二多输入逻辑门电路; 第二多输入逻辑门电路的输出端连接到第n DFF电路的数据输入端，并且其中所有上述连接使用差分信号。

2. 发明公开

EP1626501A4 VARIABLE DIVISION METHOD AND VARIABLE DIVIDER 有权
标题翻译：可变分割方法和可变分频器
公开(公告)号：EP1626501A4
公开(公告)日：2006-08-02
申请号：EP04733432
申请日：2004-05-17
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： HARADA MITSURU , YAMAGISHI AKIHIRO
IPC分类号： H03K23/66
CPC分类号： H03K23/667 , H03K23/662
摘要： A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of a reverse/non-reverse device (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the reverse/non-reverse device (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the reverse/non-reverse device (304). The fixed divider (305) divides the clock signal before division from the reverse/non-reverse device (304) according to the rise edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the rise edge of the input clock signal).

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