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1. 发明公开

EP0892352A1 Computer system with a bus having a segmented structure 失效
标题翻译：总线系统
公开(公告)号：EP0892352A1
公开(公告)日：1999-01-20
申请号：EP97830370.9
申请日：1997-07-18
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio , Zulian, Aimone
IPC分类号： G06F13/40 , G06F13/364
CPC分类号： G06F13/364 , G06F13/4031
摘要： Computer system (100) comprising a communication bus (105), a plurality of units (U1-U4) connected to the bus (105), in which the bus (105) includes a plurality of bus segments (B1-B4), each bus segment (B(i)) being concatenated with at least one adjacent bus portion (B(i-1), B(i+1)) by means of buffer registers (Br(i-1), Bl(i)) to transfer a data item from the adjacent bus segment (B(i-1), B(i+1)) to the bus portion (Bi), the computer system (100) further comprising an arbitration unit (160) to control, for each bus segment (Bi), the simultaneous access to the different segments, in a mutually exclusive way, by the units (Ui) connected to each of the segments (Bi) and by the buffers for concatenation of each of the segments with at least one adjacent segment.
摘要翻译：计算机系统（100），包括通信总线（105），连接到总线（105）的多个单元（U1-U4），其中总线（105）包括多个总线段（B1-B4）总线段（B（i））通过缓冲寄存器（Br（i-1），B1（i））与至少一个相邻总线部分（B（i-1），B 将数据项从相邻的总线段（B（i-1），B（i + 1））传送到总线部分（Bi），计算机系统（100）还包括一个仲裁单元（160）对于每个总线段（Bi），以相互排斥的方式，通过连接到每个段（Bi）的单元（Ui）和用于每个段的级联的缓冲器同时访问不同的段，最少一个相邻的段。

2. 发明授权

EP0249128B1 TTL technology digital timing unit 失效
标题翻译： TTL技术数字时序单元
公开(公告)号：EP0249128B1
公开(公告)日：1992-09-09
申请号：EP87107952.1
申请日：1987-06-02
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F1/04
CPC分类号： H03K23/662 , G06F1/06 , H03K23/68

3. 发明公开

EP0777182A1 A memory access limiter for random access dynamic memories 有权转让
标题翻译：随机存取动态存储器的存储器访问限制器
公开(公告)号：EP0777182A1
公开(公告)日：1997-06-04
申请号：EP95830495.8
申请日：1995-11-28
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G11C11/4074 , G06F1/3225 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A memory access limiter for random access dynamic memory of data processing systems formed by several modules (MM1, ... MMN) which can be independently activated in partial temporal superimposition, each by a memory start command (START.M), comprising a bidirectional counter (3, 15) which periodically increments at a constant period defined by a clock signal (CLK), by a value representative of the electrical charge delivered by a power supply (1) to an output buffer capacitor (2) and decrements, at each memory start command, by a value representative of the electrical charge drained at each memory operation activated by the memory start command, a predetermined decremented count state of the counter identifying a maximum admissible discharge condition of the buffer capacitor below which it is necessary to inhibit any further activation of the memory until the count state of the counter is no longer below the predetermined count state.
摘要翻译：一种用于数据处理系统的随机存取动态存储器的存储器访问限制器，所述数据处理系统由多个模块（MM1，...，MMN）形成，所述模块可以在部分时间叠加中独立地激活，每个模块由存储器启动命令（START.M）计数器（3,15），其以由时钟信号（CLK）限定的恒定周期周期性地增加表示由电源（1）传送到输出缓冲电容器（2）的电荷的值，并且在每个存储器启动命令通过代表在由存储器启动命令激活的每个存储器操作时排出的电荷的值，计数器的预定减量计数状态识别缓冲电容器的最大允许放电条件，在该最大允许放电条件下，必须抑制存储器的任何进一步激活，直到计数器的计数状态不再低于预定的计数状态。

4. 发明公开

EP0626778A1 A method and apparatus for improving the display of greys in a two-tone digitised image 失效
标题翻译： Verfahren undGerätzur verb desserten Grauwiedergabe in zweitondigitalisierten Bildern。
公开(公告)号：EP0626778A1
公开(公告)日：1994-11-30
申请号：EP93830177.7
申请日：1993-04-26
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： H04N1/40
CPC分类号： H04N1/4055
摘要： A method and associated apparatus for enhancing the display or print of greys in a two-tone digitised image consisting of storing a portion of a binary image map including a central bit under examination to be displayed and in testing if the said central bit is representative of an isolated dot or whether in a region around the said central bit in one of a plurality of predetermined directions there is an isolated dot at a predetermined distance from the said central bit, to display the central bit as a dot of reduced dimensions in such a way as to convert the display of an isolated dot in the display into a plurality of smaller dots with aggregate areas equivalent to the isolated dot and distributed around the location of the isolated dot identified from the image map.
摘要翻译：一种用于增强双色数字化图像中的灰度的显示或打印的方法和相关装置，包括存储包括正被检查的中心位的二进制图像映射的一部分以被显示，以及如果所述中心位是一个孤立点，或者在多个预定方向中的一个周围围绕所述中心位置的区域中是否存在距离所述中心位置预定距离处的孤立点，以将中心位显示为这样的尺寸减小的点将显示器中的孤立点的显示转换成具有与孤立点相当的聚集区域的多个较小点并分布在从图像映射图识别的孤立点的位置周围的方式。

5. 发明公开

EP0332910A3 Memory system having predictive module selection 失效
标题翻译：具有预测模块选择的存储器系统
公开(公告)号：EP0332910A3
公开(公告)日：1991-03-27
申请号：EP89103357.3
申请日：1989-02-25
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio , Porro, Enrico
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0215
摘要： Memory system comprising a plurality of memory modules, wherein the selection of one among the memory modules is performed in preselection as to the memory activation for a memory access operation , on the basis of the previously performed selection of the same module for a preceding memory access operation and wherein, in case the performed preselection is not the appropriate one, the appropriate selection is first performed and then the memory access operation is "retried".

6. 发明公开

EP0923032A1 Method for transferring data in a multiprocessor computer system with crossbar interconnecting unit 失效
标题翻译：方法um um um em em em em agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen agen
公开(公告)号：EP0923032A1
公开(公告)日：1999-06-16
申请号：EP97830656.1
申请日：1997-12-11
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio , Grassi, Antonio
IPC分类号： G06F13/00
CPC分类号： G06F13/1663 , G06F12/0813 , G06F13/1657 , G06F13/4022
摘要： Method (T1-T27) for transferring data in a computer system comprising a plurality of processors and a shared memory, at least one of the processors having a cache memory for storing corresponding data of the shared memory, a plurality of data channels to each of which at least one of the said processors is connected, and means for selectively interconnecting the data channels, the method comprising the steps of requesting (T1-T5) the reading of a data element from the shared memory by a requesting processor, and in the case (T5-T12) in which the requested data element is present in modified form in the cache memory of an intervening processor, transferring (T14-T26) the modified data element from the intervening processor to the interconnecting means and subsequently (T20-T27) to the requesting processor, in which the interconnecting means are granted (T14) access to the data channel corresponding to the requesting processor before the modified data element is available (T19) in the interconnecting means.
摘要翻译：用于在包括多个处理器和共享存储器的计算机系统中传送数据的方法（T1-T27），所述处理器中的至少一个具有用于存储共享存储器的相应数据的高速缓存存储器，所述处理器中的至少一个被连接，以及用于选择性地互连数据信道的装置，所述方法包括以下步骤：由请求处理器请求（T1-T5）从共享存储器读取数据元素;以及在（T5-T12），其中所请求的数据元素以修改的形式存在于中间处理器的高速缓冲存储器中，将修改的数据元素从中间处理器传送（T14-T26）到互连装置，随后（T20-T27））到所述请求处理器，其中所述互连装置被授权（T14）对所述修改的数据元素可用之前对应于所述请求处理器的数据信道（T19）进行访问（T19）连接方式。

7. 发明授权

EP0332910B1 Memory system having predictive module selection 失效
标题翻译：存储装置，包括预测所述块选择。
公开(公告)号：EP0332910B1
公开(公告)日：1994-07-06
申请号：EP89103357.3
申请日：1989-02-25
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio , Porro, Enrico
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0215

8. 发明公开

EP0437712A3 Tandem cache memory 失效
标题翻译：串联高速缓冲存储器
公开(公告)号：EP0437712A3
公开(公告)日：1991-11-13
申请号：EP90122942.7
申请日：1990-11-30
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F12/08
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0859 , G06F12/0862 , G06F12/0897
摘要： Tandem cache memory comprising a first cache for storing a plurality of instructions more recently requested by a processor and for providing them to the processor, following a new request, without need to fetch them from a working memory and a second cache for reading from the working memory and storing a plurality of prefetched instruction blocks having subsequent addresses in increasing order relative to a current instruction requested for execution by the processor and for providing any one of the prefetched instruction blocks to both the processor and the first cache on processor request, if the processor requests an instruction which is not in the first cache but is stored in the second cache.
摘要翻译：串联高速缓冲存储器包括第一高速缓冲存储器，用于存储处理器最近请求的多个指令，并且用于在新请求之后将它们提供给处理器，而不需要从工作存储器中取出它们，并且第二高速缓冲存储器用于从工作中读取存储并存储多个预取指令块，所述预取指令块具有相对于请求由所述处理器执行的当前指令递增的顺序的后续地址，并且用于在处理器请求时将所述预取指令块中的任何一个提供给所述处理器和所述第一高速缓存处理器请求不在第一高速缓存中但存储在第二高速缓存中的指令。

9. 发明公开

EP0278415A3 Memory system and related error detection and correction apparatus 失效
标题翻译：存储器系统及相关错误检测和校正装置
公开(公告)号：EP0278415A3
公开(公告)日：1990-08-01
申请号：EP88101668.7
申请日：1988-02-05
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： Memory system and related error detection and correction apparatus wherein the memory, independently on its parallelism, is organized in modules having 1 byte parallelism, each module having a section with 5 bit parallelism for storing SEC-DED codes related to the information stored in the module and wherein a fast memory, addressed with the information codes and the related SEC-DED codes read out from a memory module produces in output an information code, corrected as a function of the SEC-DED code, a parity check bit for the corrected information code and further bits indicative of a corrected single error and uncorrectable multiple error.

10. 发明公开

EP0249128A3 TTL technology digital timing unit 失效
标题翻译： TTL技术数字时间单位
公开(公告)号：EP0249128A3
公开(公告)日：1989-05-10
申请号：EP87107952.1
申请日：1987-06-02
申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.
发明人： Zulian, Ferruccio
IPC分类号： G06F1/04
CPC分类号： H03K23/662 , G06F1/06 , H03K23/68
摘要： Timing unit for generating a timing signal for synchronous microprocessors (such as microprocessor 68020) in which an oscillator generates a base frequency equal to four times the timing frequency for the microprocessor, a frequency divider divides the base frequency by four and provides such timing frequency, and a shift register clocked by the base frequency and receiving in input a timing signal in output from the frequency divider, generates a mask signal,which is selectively applied to a control input of the frequency divider, depending on presence of one or more control signals, to inhibit the switching of the frequency divider thereby introducing in the phases of the timing frequency wait states equal to 1/4 (or mutliple thereof) of the timing frequency.

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