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2. 发明公开

EP1626501A1 VARIABLE DIVISION METHOD AND VARIABLE DIVIDER 有权
标题翻译：变量分割法和变量分割器
公开(公告)号：EP1626501A1
公开(公告)日：2006-02-15
申请号：EP04733432.1
申请日：2004-05-17
申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION
发明人： HARADA, Mitsuru NTT Intellectual Property Center , YAMAGISHI, Akihiro NTT Int. Property Center
IPC分类号： H03K23/00
CPC分类号： H03K23/667 , H03K23/662
摘要： A feedback path (307) is formed between an output (310c) of a fixed divider (305) and a control terminal (310b) of an inverting/noninverting unit (304). A connection device (306) is arranged on the feedback path (307). The feedback path (307) is connected/disconnected according to the level of the control signal M from outside, thereby switching the number of divisions. The delay time of the signal given to the input terminal (310a) of the inverting/noninverting unit (304) to pass through the feedback path (307) and return to the control terminal (310b) is set greater than the pulse width of the input clock signal. A small pulse input invalidating function is provided in the fixed divider (305). Alternatively, a small pulse output prohibiting function is provided in the inverting/noninverting unit (304). The fixed divider (305) divides the clock signal before division from the inverting/noninverting unit (304) according to the leading edge of the clock pulse of the normal pulse width in the signal (a change point corresponding to the leading edge of the input clock signal).
摘要翻译：反馈路径（307）形成在固定分频器（305）的输出（310c）和反相/非反相单元（304）的控制端子（310b）之间。连接装置（306）被布置在反馈路径（307）上。反馈路径（307）根据来自外部的控制信号M的电平进行连接/断开，从而切换分割数。赋予反相/非反相单元（304）的输入端（310a）以通过反馈路径（307）并返回到控制端（310b）的信号的延迟时间设置为大于输入时钟信号。在固定分频器（305）中提供小脉冲输入无效功能。或者，在反相/非反相单元（304）中设置小脉冲输出禁止功能。固定分频器（305）根据信号中的正常脉冲宽度的时钟脉冲的前沿（与输入的前沿相对应的变化点）将来自反相/同相单元（304）的分频之前的时钟信号分频时钟信号）。

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