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1. 发明授权

EP2478637B1 HIGH RESOLUTION OUTPUT DRIVER 有权转让
标题翻译：高分辨率输出驱动器
公开(公告)号：EP2478637B1
公开(公告)日：2018-03-07
申请号：EP10816291.8
申请日：2010-09-14
申请人： Rambus Inc.
发明人： AMIRKHANY, Amir , HUANG, Chaofeng , KAVIANI, Kambiz , DETTLOFF, Wayne, D. , CHANG, Kun-Yung
IPC分类号： H03K17/687 , H03F3/26 , G06F13/40 , H03F3/45 , H03M1/06 , H03M1/74 , H03M1/80 , H04L25/02 , H04L25/03 , H03K19/00 , H03K19/0175 , H03M1/10
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such "differential" or "non-uniform" sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested "DAC within a DAC" arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.

2. 发明公开

EP3248221A1 CONTINUOUS DIFFUSION CONFIGURABLE STANDARD CELL ARCHITECTURE 审中-公开
标题翻译：连续扩散配置的标准单元架构
公开(公告)号：EP3248221A1
公开(公告)日：2017-11-29
申请号：EP16702619.4
申请日：2016-01-13
申请人： QUALCOMM Incorporated
发明人： SAHU, Satyanarayana , PUCKETT, Joshua Lance , KWON, Ohsang , GOODALL III, William James , BOWERS, Benjamin John
IPC分类号： H01L27/118 , H03K19/0175 , H03K19/177 , H03K19/20 , H01L27/02
CPC分类号： H03K19/017581 , H01L27/0207 , H01L27/11807 , H01L2027/11874 , H03K19/17728 , H03K19/17736 , H03K19/20
摘要： At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

3. 发明公开

EP2860626A1 PLD editor and method for editing PLD code 有权
标题翻译： PLD-Editor und Verfahren zum Editieren von PLD-Codes
公开(公告)号：EP2860626A1
公开(公告)日：2015-04-15
申请号：EP14188472.6
申请日：2014-10-10
申请人： Rockwell Automation Technologies, Inc.
发明人： Song, Tao , Wei, Zhen , Malaspina, Fabio , Li, Hongrui , Chen, Zhiyan
IPC分类号： G06F9/44
CPC分类号： G06F17/5054 , G06F8/34 , H03K19/017581 , H03K19/173
摘要： A PLD editor and method for editing PLD code to be programmed into a PLD are provided. The PLD editor includes an interface, a storage system, and a processing system configured to obtain a PLD code, with the PLD code comprising one or more logic instruction blocks and corresponding block parameters for each logic instruction block, with the PLD code being intended for programming into the PLD, compare the one or more logic instruction blocks of the PLD code to a subset of the library of logic instruction blocks applicable to the PLD according to the library of PLD devices, determine inconsistent logic instruction blocks of the one or more logic instruction blocks, indicate the inconsistent logic instruction blocks, and correct the inconsistent logic instruction blocks using the subset of the library of logic instruction blocks.
摘要翻译：提供了一种用于编辑要编程到PLD中的PLD编码的PLD编辑器和方法。 PLD编辑器包括接口，存储系统和处理系统，其被配置为获得PLD代码，其中PLD代码包括用于每个逻辑指令块的一个或多个逻辑指令块和相应的块参数，PLD代码旨在用于编程到PLD中，根据PLD设备库将PLD代码的一个或多个逻辑指令块与适用于PLD的逻辑指令块的子集进行比较，确定一个或多个逻辑的不一致的逻辑指令块指令块指示不一致的逻辑指令块，并使用逻辑指令块库的子集来校正不一致的逻辑指令块。

4. 发明公开

EP2765474A1 Clock buffer 有权
标题翻译： Taktpuffer
公开(公告)号：EP2765474A1
公开(公告)日：2014-08-13
申请号：EP13154865.3
申请日：2013-02-12
申请人： NXP B.V.
发明人： Sharma, Vibhu , Meijer, Rinze , Pineda de Gyvez, José
IPC分类号： G06F1/10 , H03K19/0175
CPC分类号： H03K19/0016 , G06F1/10 , H03K19/017581 , H03K19/018521
摘要： A tuneable buffer circuit for use in a clock tree has multiple buffers (40, 42) in parallel, each buffer having a grounding function (48), and also a bypass switch (46) in parallel with the buffers (40, 42). The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.
摘要翻译：用于时钟树的可调谐缓冲电路具有并联的多个缓冲器（40,42），每个缓冲器具有接地功能（48），以及与缓冲器（40,42）并联的旁路开关（46）。该电路具有连接到电路中的一个缓冲器的正常模式，多个缓冲器的并联第一低电压模式并联而没有接地功能，缓冲器的第二低电压模式并联到接地功能和旁路模式。

5. 发明公开

EP2226941A2 Programmable high-speed I/O interface 有权
标题翻译： Programmierbare Hochgeschwindigkeits-E / A-Schnittstelle
公开(公告)号：EP2226941A2
公开(公告)日：2010-09-08
申请号：EP09013169.9
申请日：2002-08-28
申请人： Altera Corporation
发明人： Wang, Boonie I. , Sung, Chiakang , Huang, Joseph , Nguyen, Khai , Pan, Philip
IPC分类号： H03K19/177 , H03K19/0185
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： The present application comprises an integrated circuit comprising a differential input buffer (791) having a first input coupled to a first pad (710,1210) and a second input coupled to a second pad (720,1220); a first single-ended input buffer (751) having an input coupled to the first pad (720,1220); a second single-ended input buffer (756) having an input coupled to the second pad (720,1220);a first single-ended output buffer (771) having an output coupled to the first pad (710,1210); a second single-ended output buffer (776) having an output coupled to the second pad (720,1220); a serial-to-parallel converter (725) having an input coupled to an output of the differential input buffer (791); and a parallel-to-serial converter (715) having an output coupled to an input of the first single-ended output buffer (771).
The present application further comprises a method of providing and receiving signals.
摘要翻译：本申请包括集成电路，其包括具有耦合到第一焊盘（710,1210）的第一输入和耦合到第二焊盘（720,1220）的第二输入的差分输入缓冲器（791）; 具有耦合到所述第一焊盘（720,1220）的输入的第一单端输入缓冲器（751）; 具有耦合到所述第二焊盘（720,1220）的输入的第二单端输入缓冲器（756）;具有耦合到所述第一焊盘（710,1210）的输出的第一单端输出缓冲器（771）; 具有耦合到所述第二焊盘（720,1220）的输出的第二单端输出缓冲器（776）; 具有耦合到差分输入缓冲器（791）的输出的输入的串并转换器（725）; 以及具有耦合到第一单端输出缓冲器（771）的输入的输出的并行到串行转换器（715）。本申请还包括提供和接收信号的方法。

6. 发明公开

EP2146433A2 Dispositif de sauvegarde de la configuration de terminaux d'un circuit intègre, et procédé de mise en action du dispositif 有权
标题翻译：用于备份的集成电路和方法的终端的配置用于激活该设备的装置，
公开(公告)号：EP2146433A2
公开(公告)日：2010-01-20
申请号：EP09164952.5
申请日：2009-07-08
申请人： EM Microelectronic-Marin SA
发明人： Théoduloz, Yves , Jaeggi, Hugo , Plavec, Lubomir
IPC分类号： H03K19/00 , G06F1/00
CPC分类号： H03K19/017581 , G06F1/3203 , H03K19/018585
摘要： Le dispositif (1) du circuit intégré permet de sauvegarder la configuration de terminaux de sortie (O, S P ) dudit circuit intégré dans un mode basse consommation. Pour ce faire, le dispositif comprend plusieurs unités à décalage de niveau de tension (2, 2', 2", 2"') et un étage de sortie (3) relié à chaque sortie des unités à décalage du niveau et relié à au moins une plage de contact externe (S P ) dudit circuit intégré. Chaque unité à décalage du niveau comprend un étage d'entrée alimenté sous une tension régulée interne (V REC ) et une partie de transfert d'un état d'une fonction spécifique en sortie, qui est alimentée sous une tension d'alimentation (V DD ) du circuit intégré. Chaque unité à décalage de niveau comprend également une cellule mémoire en sortie alimentée par la tension d'alimentation, pour mémoriser l'état de sortie d'une fonction spécifique de l'unité à décalage de niveau dans un mode de repos du circuit intégré où la tension régulée est coupée.
摘要翻译：所述装置（1）具有的电压电平与输出（O）连接到三态缓冲器（4）和P沟道和N沟道金属氧化物的栅极移位单元（2,2“ 2' ，2‘’”）半导体晶体管分别的输出级（3）中，（PS，NS）。各移位单元具有存储单元所做的是由电源电压供电，并且由存储信号（L-S）为在上集成电路其余模式中的移动单元的特定功能的输出状态的存储的集成的，其中调节的电压控制电路被中断。因此独立claimsoft被包括为用于致动到外部接触焊盘和输出端子配置保护装置的方法。

7. 发明授权

EP1294099B1 Programmable High-Speed I/O Interface 有权
标题翻译：可编程快速输入/输出接口
公开(公告)号：EP1294099B1
公开(公告)日：2007-09-19
申请号：EP02255977.7
申请日：2002-08-28
申请人： ALTERA CORPORATION
发明人： Wang, Bonnie I. , Sung, Chiakang , Huang, Joseph , Nguyen, Khai , Pan, Philip
IPC分类号： H03K19/177 , H03K19/0185
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788

8. 发明公开

EP1294097A3 Input/output buffer supporting multiple I/O standards 失效
标题翻译： Eangangs- / Ausgangspuffer fel eine Vielzahl von Standards
公开(公告)号：EP1294097A3
公开(公告)日：2004-11-03
申请号：EP02027043.5
申请日：1997-08-28
申请人： Xilinx, Inc.
发明人： Goetting, Erich, F. , Frake, Scott, O. , Kondapalli, Venu, M.
IPC分类号： H03K19/0185
CPC分类号： H03K19/018585 , H03K19/017581
摘要： An input/output I/O block structure for a programmable logic device, the structure including: a plurality of I/O blocks grouped into sets of I/O blocks, each set having a separate output supply voltage; a set of two or more output supply voltage pads associated with each set of I/O blocks; and configurable means for connecting each set of I/O blocks to a respective set of the output supply voltage pads.
摘要翻译：一种用于可编程逻辑器件的输入/输出I / O块结构，该结构包括：分组为I / O块组的多个I / O块，每组具有单独的输出电源电压; 一组与每组I / O块相关联的两个或更多个输出电源电压垫; 以及用于将每组I / O块连接到相应的输出电源电压焊盘组的可配置装置。

9. 发明公开

EP1093226A1 Electronic driver circuit with multiplexer for alternatively driving a load or a busline, and method 有权
标题翻译：电子驱动器电路多路转换器，用于选择性地控制负载n或一个总线上，和相应的方法
公开(公告)号：EP1093226A1
公开(公告)日：2001-04-18
申请号：EP00120528.5
申请日：2000-09-20
申请人： MOTOROLA, INC.
发明人： Specks, Will , Strecker, Markus , Erckert, Ricardo , Vareilhias, Francoise
IPC分类号： H03K19/0175 , B60R1/06 , B60R16/02
CPC分类号： H03K19/017581 , Y10T307/281 , Y10T307/391
摘要： An electronic system (101/102) for use in a car has an electronic control unit (10) and, in the alternative, either a passive load (11) or an active logic (12) attached thereto. The control unit (10) comprises a push-pull arrangement (20) which can provide drive signals for the load (11) as well as for the logic (12), a multiplexer (45) to alternatively forward a load drive signal of a bus signal to the arrangement (20), and a register (90) to store a mode signal. Further, the control unit (10) automatically determines whether either the load (11) or the logic (12) is attached by analyzing electrical parameters.
摘要翻译：用于在汽车上使用的电子系统（101/102）具有电子控制单元（10），并且在替代方案中，无论与其相连的无源负载（11）或以有效逻辑（12）。所述控制单元（10）包括推挽式装置（20），它可以为负载提供（11）的驱动信号，以及用于所述逻辑（12），多路复用器（45）交替地向前一个的负载驱动信号总线信号的装置（20）和寄存器（90），以存储的模式信号。此外，控制单元（10）自动地确定是否任一负载（11）或所述逻辑（12）是通过分析电参数附接。

10. 发明授权

EP0610426B1 SAMPLING BUFFER FOR FIELD PROGRAMMABLE INTERCONNECT DEVICE 失效
标题翻译：扫描缓冲用户可编程连线装置
公开(公告)号：EP0610426B1
公开(公告)日：1999-08-25
申请号：EP92924152.9
申请日：1992-10-29
申请人： I-Cube, Inc.
发明人： HSIEH, Wen-Jai , JENQ, Yih-Chyun , HORNG, Chi-Song , LOFSTROM, Keith
IPC分类号： G06F13/00 , G06F13/40 , H03K19/0175
CPC分类号： G06F13/4004 , H03K19/017581 , H03K19/01759
摘要： A bi-directional buffer (94) includes first (100) and second (102) unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer (100) pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer (100) temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer (102) pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer (102) temporarily supplies a high charging current to the first bus to quickly pull it up.

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