会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明公开
    • DISPLAY DEVICE
    • EP3223283A3
    • 2018-02-21
    • EP17168951.6
    • 2007-09-11
    • Semiconductor Energy Laboratory Co., Ltd.
    • Umezaki, AtsushiMiyake, Hiroyuki
    • G11C19/28G09G3/36
    • H01L27/124G09G3/2092G09G3/3266G09G3/3674G09G3/3677G09G2300/0809G09G2310/0205G09G2310/0248G09G2310/0286G09G2310/0289G09G2310/0291G09G2310/061G09G2320/0646G09G2320/0666G11C19/28H01L27/0207H01L27/1222H01L27/1225
    • A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.
    • 7. 发明公开
    • DISPLAY DEVICE
    • 显示设备
    • EP3223283A2
    • 2017-09-27
    • EP17168951.6
    • 2007-09-11
    • Semiconductor Energy Laboratory Co., Ltd.
    • Umezaki, AtsushiMiyake, Hiroyuki
    • G11C19/28G09G3/36
    • H01L27/124G09G3/2092G09G3/3266G09G3/3674G09G3/3677G09G2300/0809G09G2310/0205G09G2310/0248G09G2310/0286G09G2310/0289G09G2310/0291G09G2310/061G09G2320/0646G09G2320/0666G11C19/28H01L27/0207H01L27/1222H01L27/1225
    • A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.
    • 一种半导体器件,包括:第一晶体管; 第二晶体管; 第三晶体管; 第四晶体管; 第五晶体管; 第六晶体管; 第七晶体管; 第八晶体管; 以及第九晶体管,其中所述第一晶体管的源极和漏极中的一个直接连接到第一布线,其中所述第一晶体管的源极和漏极中的另一个直接连接到第二布线,其中, 所述第二晶体管的源极和漏极直接连接到所述第一晶体管的栅极,其中所述第二晶体管的栅极直接连接到第三布线,其中所述第三晶体管的源极和漏极中的一个直接连接到 第四布线,其中第三晶体管的源极和漏极中的另一个直接连接到第一晶体管的栅极,其中第四晶体管的源极和漏极中的一个直接连接到第四布线,其中, 第四晶体管的源极和漏极中的另一个直接连接到第一晶体管的栅极,其中第四晶体管的栅极直接连接到第五布线,其中, 第五晶体管的源极和漏极直接连接到第四布线,其中第五晶体管的源极和漏极中的另一个直接连接到第三晶体管的栅极,其中第五晶体管的栅极直接连接到 连接到第一晶体管的栅极,其中第六晶体管的源极和漏极中的一个直接连接到第六布线,其中第六晶体管的源极和漏极中的另一个直接连接到第三晶体管的栅极 其中所述第六晶体管的栅极直接连接到所述第六布线,其中所述第七晶体管的源极和漏极中的一个直接连接到所述第六布线,其中所述第七晶体管的源极和漏极中的另一个 直接连接到第三晶体管的栅极。 其中第八晶体管的源极和漏极中的一个直接连接到第七布线,其中第八晶体管的源极和漏极中的另一个直接连接到第三晶体管的栅极,其中源极和漏极中的一个 第九晶体管的漏极直接连接到第七布线,其中第九晶体管的源极和漏极中的另一个直接连接到第三晶体管的栅极,并且其中第九晶体管的栅极直接连接到 第七条接线。
    • 9. 发明公开
    • Display apparatus and control method thereof
    • Anzeigevorrichtung und Steuerungsverfahrendafür
    • EP2712195A3
    • 2016-10-26
    • EP13180450.2
    • 2013-08-14
    • Samsung Electronics Co., Ltd
    • Jo, Young-hunKim, Sung-sooSeong, Hwa-seok
    • H04N13/00H04N13/04
    • H04N13/324G09G3/003G09G3/3611G09G2310/061G09G2320/0252G09G2320/0285H04N13/122H04N13/133H04N13/144H04N13/341H04N13/398
    • A display apparatus which outputs a stereoscopic image and a control method thereof, the display apparatus includes: an image input part which receives left and right eye image frames; an image processor which generates a left eye image interpolation frame by using a gradation difference of areas between a previous right eye image frame of the left eye image frame and the left eye image frame and generates a right eye image interpolation frame by using a gradation difference of areas between a previous left eye image frame of the right eye image frame and the right eye image frame; a display which displays the left eye image interpolation frame, the left eye image frame, the right eye image interpolation frame, and the right eye image frame sequentially according to a preset order; and a controller which controls the image processor to generate the left and right eye image interpolation frames.
    • 输出立体图像的显示装置及其控制方法,所述显示装置包括:图像输入部,其接收左眼图像帧和右眼图像帧; 图像处理器,其通过使用左眼图像帧的先前右眼图像帧和左眼图像帧之间的区域的灰度差产生左眼图像内插帧,并且通过使用灰度差异来生成右眼图像内插帧 在右眼图像帧的先前左眼图像帧和右眼图像帧之间的区域; 根据预设顺序依次显示左眼图像内插帧,左眼图像帧,右眼图像内插帧和右眼图像帧的显示器; 以及控制器,其控制图像处理器以生成左眼和右眼图像内插帧。