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    • 8. 发明公开
    • High-impedance circuit
    • Schaltung mit hoher Impedanz。
    • EP0621688A3
    • 1995-12-27
    • EP94106012.1
    • 1994-04-18
    • SANYO ELECTRIC Co., Ltd.
    • Hosoya, Nobukazu
    • H03H11/46H04N5/46
    • H04N9/642H03F3/45071H03F3/45085H03F2203/45576H03F2203/45594H03F2203/45604H03F2203/45612H03H11/46H04N5/46
    • A high-impedance circuit includes a differential pair circuit (Tr6,Tr7) composed of a first transistor and a second transistor, and a buffer circuit. The buffer circuit includes an NPN type transistor pair (Tr3,Tr5,Tr8,Tr9) composed of a cascade connection of NPN type transistors, and a PNP type transistor pair (Tr2,Tr4,Tr10,Tr11) composed of a cascade connection of PNP type transistors, and bases of the NPN type transistors and bases of PNP type transistors respectively corresponding to the NPN type transistors are connected to each other, respectively so as to constitute current mirror circuits. An output of the differential pair circuit is connected to a cascade connection point of the NPN type transistor pair (Tr3,Tr5,Tr8,Tr9), and an emitter of an NPN type transistor (Tr5,Tr8) included in the NPN type transistor pair is connected to the ground via a constant current source (I2,I4), and the emitter is connected to bases of the first transistor (Tr6) and the second transistor (Tr7) via resistors (R1), respectively. Therefore, the output of the differential pair circuit is fed-back to inputs of the differential pair circuit, i.e. the bases of the first transistor and the second transistor as base currents.
    • 高阻抗电路包括由第一晶体管和第二晶体管构成的差分对电路和缓冲电路。 缓冲电路包括由NPN型晶体管的级联连接的NPN型晶体管对和由PNP型晶体管的级联连接构成的PNP型晶体管对,以及NPN型晶体管和PNP型晶体管的基极分别对应于 NPN型晶体管分别相互连接,构成电流镜电路。 差分对电路的输出端连接到NPN型晶体管对的级联连接点,NPN型晶体管对中包含的NPN型晶体管的发射极通过恒流源与地相连,发射极 分别经由电阻器连接到第一晶体管和第二晶体管的基极。 因此,差分对电路的输出被反馈到差分对电路的输入端,即第一晶体管和第二晶体管的基极作为基极电流。