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1. 发明公开

EP3261250A1 AMPLIFICATION CIRCUIT 有权
标题翻译：功率放大电路
公开(公告)号：EP3261250A1
公开(公告)日：2017-12-27
申请号：EP16885458.6
申请日：2016-07-19
申请人： Shenzhen Goodix Technology Co., Ltd.
发明人： ZHANG, Mengwen
IPC分类号： H03F3/45
CPC分类号： H03F1/0205 , H03F1/301 , H03F1/32 , H03F3/005 , H03F3/187 , H03F3/45183 , H03F3/45188 , H03F3/45192 , H03F3/45475 , H03F3/45659 , H03F3/45699 , H03F3/45762 , H03F2200/129 , H03F2200/156 , H03F2200/159 , H03F2200/18 , H03F2200/222 , H03F2200/252 , H03F2200/264 , H03F2200/471 , H03F2200/555 , H03F2203/45008 , H03F2203/45012 , H03F2203/45024 , H03F2203/45028 , H03F2203/45054 , H03F2203/45068 , H03F2203/45082 , H03F2203/45112 , H03F2203/45134 , H03F2203/45136 , H03F2203/45171 , H03F2203/45174 , H03F2203/45182 , H03F2203/45188 , H03F2203/45192 , H03F2203/45208 , H03F2203/45244 , H03F2203/45332 , H03F2203/45421 , H03F2203/45434 , H03F2203/45444 , H03F2203/45512 , H03F2203/45514 , H03F2203/45534 , H03F2203/45544 , H03F2203/45546 , H03F2203/45551 , H03F2203/45586 , H03F2203/45588 , H03F2203/45616 , H03F2203/45632 , H03F2203/45642 , H03F2203/45656 , H03F2203/45674 , H03F2203/45676
摘要： The present application provides an amplifying circuit comprising a reference voltage generating circuit, a common-mode voltage conversion circuit, a common-mode negative feedback circuit, and an amplifying sub-circuit. The reference voltage generating circuit generates a first reference voltage, a second reference voltage, and a reference common-mode voltage according to a post-stage common-mode voltage, the common-mode voltage conversion circuit converts the pre-stage output differential signal into a differential input signal according to the reference common-mode voltage, the common-mode negative feedback circuit generates a control voltage to quickly establish a common-mode negative feedback of the amplifying sub-circuit, wherein the first reference voltage and the second reference voltage are used to cancel a baseline signal of the pre-stage output differential signal. The amplifying circuit provided in the present application can eliminate the baseline signal, convert the common-mode voltage and quickly establish the common-mode negative feedback.
摘要翻译：本申请提供一种放大电路，包括参考电压产生电路，共模电压转换电路，共模负反馈电路和放大子电路。参考电压产生电路根据后级共模电压产生第一参考电压，第二参考电压和参考共模电压，共模电压转换电路将前级输出差分信号转换为根据所述参考共模电压产生差分输入信号，所述共模负反馈电路产生控制电压以快速建立所述放大子电路的共模负反馈，其中，所述第一参考电压和所述第二参考电压被用于消除前级输出差分信号的基线信号。本申请提供的放大电路可以消除基线信号，转换共模电压，快速建立共模负反馈。

2. 发明授权

EP2057735B1 DIFFERENTIAL TO SINGLE-ENDED CONVERSION CIRCUIT AND COMPARATOR USING THE CIRCUIT 有权转让
标题翻译：电路差价的不对称转换和开关使用SANTANDER比较器
公开(公告)号：EP2057735B1
公开(公告)日：2012-07-25
申请号：EP06796270.4
申请日：2006-08-28
申请人： ST-Ericsson SA
发明人： ZAMPROGNO, Marco , CONFALONIERI, Pierangelo , MINUTI, Alberto
IPC分类号： H03F3/00 , H03F3/45
CPC分类号： H03F3/005 , H03F3/45192 , H03F2203/45028 , H03F2203/45138 , H03F2203/45396 , H03F2203/45534 , H03F2203/45726
摘要： An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN') input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

3. 发明公开

EP2245737A1 DIFFERENTIAL AMPLIFIER WITH ACCURATE INPUT OFFSET VOLTAGE 审中-公开
标题翻译：一个准确的输入失调电压差动放大器
公开(公告)号：EP2245737A1
公开(公告)日：2010-11-03
申请号：EP09705930.7
申请日：2009-01-29
申请人： QUALCOMM Incorporated
发明人： DAVIERWALLA, Anosh B. , LEE, Chul Kyu , DANG, Vannam
IPC分类号： H03F3/45 , H03K5/24
CPC分类号： H03F3/45183 , H03F3/45192 , H03F3/45766 , H03F2200/453 , H03F2200/456 , H03F2203/45028 , H03F2203/45048 , H03F2203/45286 , H03F2203/45291 , H03F2203/45294 , H03F2203/45624 , H03F2203/45628 , H03K5/2481
摘要： An amplifier (209) ( with accurate input offset voltage is described. In one design, the amplifier includes first and s (312, 314) receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair (322, 324) receives a differential reference signal (Vref p, Vref n) and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal Ioutp, lout n) The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.

4. 发明公开

EP0824783A1 BALANCED DOUBLE-FOLDED CASCODE OPERATIONAL AMPLIFIER 失效
标题翻译：均衡，双重折叠KASKODENOPERATIONSVERSTÄRKER
公开(公告)号：EP0824783A1
公开(公告)日：1998-02-25
申请号：EP95931042.0
申请日：1995-08-31
申请人： ANALOG DEVICES, INCORPORATED
发明人： BUTLER, James, R.
IPC分类号： H03F3
CPC分类号： H03F3/4521 , H03F3/3067 , H03F3/45071 , H03F3/45121 , H03F2200/258 , H03F2203/45028 , H03F2203/45232 , H03F2203/45244 , H03F2203/45281 , H03F2203/45366 , H03F2203/45508 , H03F2203/45552 , H03F2203/45568
摘要： A double-folded cascode operational amplifier capable of operating with rail-to-rail common mode inputs includes two differential transistor pairs (Q1, Q2, Q6, Q7) of opposite conductivity, with an associated current source and input resistor pair for each pair of input transistors. Its gain stage (6) includes two interconnected pairs of folded cascode gain transistors (Q3, Q4, Q12, Q13) that are connected to the two pairs of input resistors so that a change in the differential input signal produces a corresponding change in the gain stage output via the resistors. An output stage (8) includes transistor-resistor circuitry to bias a pair of output transistors (Q20, Q21) in opposite directions and produce a net amplifier output at their junction. The gain transistor voltages are balanced by a voltage shifting circuit to inhibit input voltage offsets.

5. 发明授权

EP0595589B1 Differential output amplifier input stage with rail-to-rail common mode input range 失效
标题翻译：差分放大器的平衡输出与去在工作电压范围在输入共模范围
公开(公告)号：EP0595589B1
公开(公告)日：1998-01-07
申请号：EP93308504.5
申请日：1993-10-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Ryat, Marc Henri
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45121 , H03F3/45529 , H03F2203/45028 , H03F2203/45126 , H03F2203/45212 , H03F2203/45232 , H03F2203/45366 , H03F2203/45402 , H03F2203/45711

6. 发明授权

EP0415620B1 Electrical circuit 失效
标题翻译：一个电路
公开(公告)号：EP0415620B1
公开(公告)日：1997-11-05
申请号：EP90309088.4
申请日：1990-08-20
申请人： DELCO ELECTRONICS CORPORATION
发明人： Kearney, Mark B.
IPC分类号： H03F3/45
CPC分类号： H03F3/45094 , H03F2203/45011 , H03F2203/45028 , H03F2203/45076 , H03F2203/45188 , H03F2203/45212 , H03F2203/45466 , H03F2203/45476

7. 发明公开

EP0797296A2 Low voltage operational amplifier input stage and method 失效
标题翻译：输入级和方法，用于具有低的工作电压的运算放大器
公开(公告)号：EP0797296A2
公开(公告)日：1997-09-24
申请号：EP97103644.7
申请日：1997-03-05
申请人： MOTOROLA, INC.
发明人： Dotson, Robert N. , Griffith, Richard S. , Vyne, Robert L.
IPC分类号： H03F3/45
CPC分类号： H03F3/4508 , H03F3/3067 , H03F3/343 , H03F3/45076 , H03F2203/45028 , H03F2203/45182
摘要： Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0° to 70° centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) create the base drive current in transistors (18) and (24). Dependent on the input signal the AC signal path on SINK PASS THROUGH signal controls op amp output sink transistor to sink current or through current steering circuit (16) causes SOURCE PASS THROUGH signal controlling op amp output source transistor to source current. An output stage provides approximately fifty milliamps of current drive and is quiescent until the output driver is selected.
摘要翻译：低压运算放大器（10）操作在一到8伏的温度范围内0°〜70°摄氏度的的电压范围。运放输入级（12）使用N沟道耗尽型MOSFET，以提供差分输入的放大和保持恒定的跨导。源极跟随器MOSFET（13）提供在传递环单位增益AC信号，STAGE-1 OUTPUT，到电流吸收晶体管（18）的基极。吸收控制电路（14）和源控制电路（22）创建在晶体管（18）的基极驱动电流和（24）。依赖于输入信号经过信号控制上SINK PASS AC信号路径运算放大器的输出吸收晶体管吸收电流，或者通过电流控制电路（16）引起SOURCE直通信号控制运放输出源晶体管到源极的电流。输出级提供大约50毫安的电流驱动的和直到选择了输出驱动器是静止的。

8. 发明授权

EP0481630B1 High efficiency cross-coupled folded cascode circuit 失效
标题翻译：交叉耦合的共源共栅折叠以高效率。
公开(公告)号：EP0481630B1
公开(公告)日：1995-09-13
申请号：EP91309009.8
申请日：1991-10-02
申请人： ANALOG DEVICES, INCORPORATED
发明人： Butler, James R.
IPC分类号： H03F3/45 , H03F1/32
CPC分类号： H03F3/45291 , H03F1/3211 , H03F2203/45028 , H03F2203/45318 , H03F2203/45352 , H03F2203/45676

9. 发明公开

EP0595589A2 Differential output amplifier input stage with rail-to-rail common mode input range 失效
标题翻译：差分放大器的平衡输出与去在输入处的工作电压范围的共模范围。
公开(公告)号：EP0595589A2
公开(公告)日：1994-05-04
申请号：EP93308504.5
申请日：1993-10-26
申请人： SGS-THOMSON MICROELECTRONICS, INC.
发明人： Ryat, Marc Henri
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45121 , H03F3/45529 , H03F2203/45028 , H03F2203/45126 , H03F2203/45212 , H03F2203/45232 , H03F2203/45366 , H03F2203/45402 , H03F2203/45711
摘要： An amplifier having a rail-to-rail common mode input range that can be used in low voltage power supply applications includes differential input and output stages, the output stage having first and second current paths. First and second output duplicating circuits are respectively connected in parallel with the first and second current paths in the differential output stage to duplicate the differential output. A circuit for detecting a common-mode voltage difference is provided between nodes of the first and second output duplicating circuits for developing a current related to the common-mode voltage difference. A current mirror circuit is connected to receive the current related to the common-mode voltage difference for controlling the current in the first and second current paths in the differential output stage. The circuit for detecting a common-mode voltage difference between nodes of the first and second output duplicating circuits can be established by a transistor that senses only common-mode current. The transistor has a control element connected to the nodes in the output duplicating circuits and a current path to a supply voltage.
摘要翻译：具有轨到轨共模输入范围的放大器可以用于在低电压电源应用确实包括差分输入级和输出级，其具有第一和第二电流路径的输出级。第一和第二输出复制电路被连接在分别与所述差分输出级复制的差动输出的第一和第二电流路径并联。用于开发的电流相关的共模电压差，第一和第二输出复制电路的节点之间提供了一种用于检测共模电压差电路。的电流镜电路被连接以接收电流相关的共模电压差，用于控制在所述第一和第二电流路径中的电流的差分输出级。由晶体管做感官仅共模电流可以建立用于检测所述第一和第二输出复制电路的节点之间的共模电压差的电路。该晶体管具有连接到输出复制电路和一个电流路径到电源电压的节点的控制元件。

10. 发明公开

EP0481630A1 High efficiency cross-coupled folded cascode circuit 失效
标题翻译： Kreuzgekoppelte，gefaltete Kaskodenschaltung mit hohem Wirkungsgrad。
公开(公告)号：EP0481630A1
公开(公告)日：1992-04-22
申请号：EP91309009.8
申请日：1991-10-02
申请人： ANALOG DEVICES, INCORPORATED
发明人： Butler, James R.
IPC分类号： H03F3/45 , H03F1/32
CPC分类号： H03F3/45291 , H03F1/3211 , H03F2203/45028 , H03F2203/45318 , H03F2203/45352 , H03F2203/45676
摘要： A differential input circuit has an input stage with a pair of differentially biased input transistors (Q1,Q2) connected to supply current through respective load impedances (R1,R2), and a gain stage with a second pair of transistors (Q3,Q4) connected to supply additional currents to the load impedances (R1,R2) to keep the impedance currents constant over variations in the input voltage levels. A cross-coupled cascode circuit (Q8,Q9,6,8) connected between the gain stage transistors (Q3,Q4) and the load impedances (R1,R@) compensates for inaccuracies in the load impedance currents which occur during dynamic operation of the circuit, and thus enhances gain, linearity and the current transfer efficiency between the two stages.
摘要翻译：差分输入电路具有输入级，其具有连接到通过相应负载阻抗（R1，R2）提供电流的一对差分偏置输入晶体管（Q1，Q2），以及具有第二对晶体管（Q3，Q4）的增益级，连接以向负载阻抗（R1，R2）提供额外的电流，以使阻抗电流恒定在输入电压电平的变化上。连接在增益级晶体管（Q3，Q4）和负载阻抗（R1，R @）之间的交叉耦合共源共栅电路（Q8，Q9,6,8）补偿在动态运行期间发生的负载阻抗电流的不准确性电路，从而增强了两级之间的增益，线性度和电流传输效率。

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