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1. 发明授权

EP0982779B1 Memory structure in ferroelectric nonvolatile memory and readout method therefor 有权
标题翻译：在强电介质非易失性存储器和相关的读出方法的存储器结构
公开(公告)号：EP0982779B1
公开(公告)日：2007-11-14
申请号：EP99116504.4
申请日：1999-08-23
申请人： Semiconductor Technology Academic Research Center
发明人： Ishiwara, Hiroshi
IPC分类号： H01L27/115 , G11C11/22
CPC分类号： H01L27/11502 , G11C11/223

2. 发明授权

EP1122882B1 Amplifier circuit 有权
标题翻译：放大器电路
公开(公告)号：EP1122882B1
公开(公告)日：2007-10-17
申请号：EP00127728.4
申请日：2000-12-18
申请人： Semiconductor Technology Academic Research Center
发明人： Wada, Kazuyuki , Takagi, Shigetaka , Fujii, Nobuo
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/301 , H03F3/45475 , H03F2200/513 , H03F2203/45028 , H03F2203/45138

3. 发明授权

EP1237092B1 Multi-processor system apparatus with a multiple stage connection arrangement 有权
标题翻译：装置用于与多级连接布置的多处理器系统
公开(公告)号：EP1237092B1
公开(公告)日：2005-12-28
申请号：EP02004651.2
申请日：2002-02-28
申请人： Semiconductor Technology Academic Research Center
发明人： Morimura, Tomohiro , Amano, Hideharu
IPC分类号： G06F15/173
CPC分类号： G06F15/17393

4. 发明公开

EP1237092A3 Multi-processor system apparatus 有权
标题翻译：装置用于多计算机系统
公开(公告)号：EP1237092A3
公开(公告)日：2004-05-19
申请号：EP02004651.2
申请日：2002-02-28
申请人： Semiconductor Technology Academic Research Center
发明人： Morimura, Tomohiro , Amano, Hideharu
IPC分类号： G06F15/173
CPC分类号： G06F15/17393
摘要： A multi-processor system apparatus allows a compiler to perform a static scheduling action easily and can conduct the transfer of data packets without collision in response to a common pattern of simultaneous access demands. Processor elements are interconnected by a multi-stage interconnection network having multiple stages. As each of switching elements in the multi-stage interconnection network is preliminarily subjected to the static scheduling action of a compiler. The multi-stage interconnection network is emulated without producing collision of data. When the transfer of packets is carried out in one clos network arrangement of the multi-stage interconnection network, the scheduling of switching elements SE0 to SE3 in the exchanger at Level 1 is determined so that a packet lost in the arbitration is transferred through the free port of any applicable one of the switching elements.

5. 发明公开

EP1122882A2 Amplifier circuit 有权
标题翻译： Verstärkerschaltung
公开(公告)号：EP1122882A2
公开(公告)日：2001-08-08
申请号：EP00127728.4
申请日：2000-12-18
申请人： Semiconductor Technology Academic Research Center
发明人： Wada, Kazuyuki , Takagi, Shigetaka , Fujii, Nobuo
IPC分类号： H03F3/45
CPC分类号： H03F3/45192 , H03F1/301 , H03F3/45475 , H03F2200/513 , H03F2203/45028 , H03F2203/45138
摘要： A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier (1), a load resistor (2) having one end connected to an output terminal of the current output amplifier and a voltage control circuit (3) having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
摘要翻译：一种半导体集成电路，包括：放大电路，包括电流输出放大器（1），一端连接到电流输出放大器的输出端的负载电阻（2）和电压控制电路（3），输入端连接到负载电阻的一端和连接到负载电阻的另一端的输出端子。放大电路的输入端作为电流输出放大器的输入端，放大电路的输出端作为负载电阻的各端。

6. 发明公开

EP1076309A1 Semiconductor computing circuit and computing apparatus 审中-公开
标题翻译： Halbleiter-Rechenschaltung和Recheneinrichtung
公开(公告)号：EP1076309A1
公开(公告)日：2001-02-14
申请号：EP00305955.7
申请日：2000-07-13
申请人： Semiconductor Technology Academic Research Center
发明人： Shibata, Tadashi , Konda, Masahiro, Itsutsubashi Dormitory , Ohmi, Tadahiro
IPC分类号： G06G7/14
CPC分类号： G06G7/14
摘要： Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage. The semiconductor computing circuit comprises: a first MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate; a second MOS transistor having a floating gate and a control gate capacitively coupled to the floating gate, and whose source electrode is connected to the source electrode of the first MOS transistor; a write circuit which, with a prescribed voltage applied to the control gates of the first and second MOS transistors, sets the potential at the floating gate of the first MOS transistor to a value equal to the first signal voltage and also sets the potential at the floating gate of the second MOS transistor equal to a value obtained by subtracting the first signal voltage from the prescribed voltage; and a difference voltage computing circuit for computing a voltage representing a value obtained by subtracting the second signal voltage from the prescribed voltage, and wherein: after setting the first and second MOS transistors by the write circuit, when the output voltage of the difference voltage computing circuit is applied to the control gate of the first MOS transistor while at the same time applying the second signal voltage to the control gate of the second MOS transistor, the absolute-value voltage representing the difference between the first signal voltage and the second signal voltage is output.
摘要翻译：公开了一种可以用简单电路实现的半导体计算电路，能够高速执行模拟计算，以计算表示第一信号电压和第二信号电压之差的绝对值电压。半导体计算电路包括：第一MOS晶体管，具有浮动栅极和电容耦合到浮动栅极的控制栅极; 具有浮置栅极和与栅极电容耦合的控制栅极的第二MOS晶体管，其源极连接到第一MOS晶体管的源极; 写入电路，其中施加到第一和第二MOS晶体管的控制栅极的规定电压将第一MOS晶体管的浮置栅极处的电位设置为等于第一信号电压的值，并且还将电位设置在第二MOS晶体管的浮置栅极等于通过从规定电压减去第一信号电压而获得的值; 以及差分电压计算电路，用于计算表示通过从规定电压减去第二信号电压而获得的值的电压，并且其中：在通过写入电路设置第一和第二MOS晶体管之后，当差分电压计算的输出电压电路施加到第一MOS晶体管的控制栅极，同时将第二信号电压施加到第二MOS晶体管的控制栅极，绝对值电压表示第一信号电压和第二信号电压之间的差被输出。

7. 发明公开

EP0848342A3 Intergrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus 失效
标题翻译：设计集成电路，数据银行装置用于集成电路设计和支持设备，用于集成电路的设计的方法
公开(公告)号：EP0848342A3
公开(公告)日：2001-01-10
申请号：EP97121676.7
申请日：1997-12-09
申请人： Semiconductor Technology Academic Research Center
发明人： Imai, Masaharu, 404, Lions-mansion-hibarigaoka , Takeuchi, Yoshinori , Siomi, Akichika , Sato, Jun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In a database(11), variety of modules which can be used as constituent elements of the object of design are registered as parametrized models, and instance generating information representing a procedure of generating (58) instances and feature estimation information representing a method for estimating (60) design features are stored every abstraction level for the various modules. A floorplan oriented design is executed by means of the database (11). That is, even at the higher level of the behavior or RT level, by means of the database (11), the design features of each module to be used for the design are estimated and the floorplan is executed (S16). On the basis of the execution result, the design features of the circuit scale, delay time, power consumption and so forth of the object of design are estimated (S18), and it is decided whether or not a design change is required (S20).

8. 发明公开

EP0982779A3 Memory structure in ferroelectric nonvolatile memory and readout method therefor 有权
标题翻译： Speicherstruktur in ferroelektrischemnichtflüchtigenSpeicher unddiesbezüglicheAuslesemethode
公开(公告)号：EP0982779A3
公开(公告)日：2000-05-17
申请号：EP99116504.4
申请日：1999-08-23
申请人： Semiconductor Technology Academic Research Center
发明人： Ishiwara, Hiroshi
IPC分类号： H01L27/115 , G11C11/22
CPC分类号： H01L27/11502 , G11C11/223
摘要： Each of memory cells of a ferroelectric nonvolatile memory includes a MOS field effect transistor (Tr) and first and second ferroelectric capacitors (C B , C A ) whose remnant polarization amounts are substantially equal to each other. One-side electrodes of the first and second ferroelectric capacitors are connected to the gate electrode of the MOS field effect transistor. Information is stored by polarizing the thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the MOS field effect transistor. Information is read out by applying a positive voltage pulse to one of the other electrodes of the first and second ferroelectric capacitors while the other one of the other electrodes is kept in the electrically floating state. Further a negative voltage pulse having an absolute value smaller than the positive voltage pulse may be applied, if necessary.
摘要翻译：铁电非易失性存储器的每个存储单元包括MOS场效应晶体管（Tr）和剩余极化量彼此基本相等的第一和第二强电介质电容器（CB，CA）。第一和第二铁电电容器的单面电极连接到MOS场效应晶体管的栅电极。信息通过相对于MOS场效应晶体管的栅电极使彼此相反的方向偏振第一和第二强电介质电容器的薄铁酸薄膜来存储。通过将正电压脉冲施加到第一和第二铁电电容器的另一个电极而另一个电极保持在电浮动状态来读出信息。此外，如果需要，可以施加绝对值小于正电压脉冲的负电压脉冲。

9. 发明公开

EP0848342A2 Intergrated circuit design method, database apparatus for designing integrated circuit and integrated circuit design support apparatus 失效
标题翻译：设计集成电路，数据银行装置用于集成电路设计和支持设备，用于集成电路的设计的方法
公开(公告)号：EP0848342A2
公开(公告)日：1998-06-17
申请号：EP97121676.7
申请日：1997-12-09
申请人： Semiconductor Technology Academic Research Center
发明人： Imai, Masaharu, 404, Lions-mansion-hibarigaoka , Takeuchi, Yoshinori , Siomi, Akichika , Sato, Jun
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： In a database(11), variety of modules which can be used as constituent elements of the object of design are registered as parametrized models, and instance generating information representing a procedure of generating (58) instances and feature estimation information representing a method for estimating (60) design features are stored every abstraction level for the various modules. A floorplan oriented design is executed by means of the database (11). That is, even at the higher level of the behavior or RT level, by means of the database (11), the design features of each module to be used for the design are estimated and the floorplan is executed (S16). On the basis of the execution result, the design features of the circuit scale, delay time, power consumption and so forth of the object of design are estimated (S18), and it is decided whether or not a design change is required (S20).
摘要翻译：在数据库（11）中，各种模块，其可以被用作生成表示生成（58）的实例和表示用于估计方法特征估计信息的程序信息设计的对象的构成要素被登记为参数化的模型，和实例（60）设计特征被存储用于各个模块的每个抽象层次。楼层平面图导向的设计是由数据库（11）的方式来执行。即，即使在行为或RT水平更高的水平，由数据库（11）的方式，将用于设计估计每个模块的设计特征和平面布局被执行（S16）。所执行的结果的基础上，电路规模的设计特点，延迟时间，功率消耗等被估计（S18）设计的目的的，并且决定是否需要改变设计（S20），

10. 发明公开

EP1473736A3 Ferroelectric non-volatile memory device 审中-公开
标题翻译：非易失性铁电存储器阵列
公开(公告)号：EP1473736A3
公开(公告)日：2006-10-04
申请号：EP04017770.1
申请日：2000-05-03
申请人： Semiconductor Technology Academic Research Center
发明人： Ishiwara, Hiroshi
IPC分类号： G11C11/22 , G11C27/02
CPC分类号： G11C11/22 , G11C11/223
摘要： A ferroelectric non-volatile memory device comprising a MOS cell transistor (Q1), two ferroelectric capacitors (C A , C B ) each of which has one terminal connected to the gate electrode of the cell transistor (Q1) and has almost the same remanent polarization, and a selector transistor (Q2) connected to the other terminal of one ferroelectric capacitor C B , wherein data is stored by polarizing the ferroelectric thin films of the capacitors in opposite directions with respect to the gate electrode of the cell transistor (Q1).

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