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1. 发明公开

EP3050103A4 NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WORKFUNCTION ON COMMON SUBSTRATE 有权
标题翻译： NICHTPLANARE I / O- UND LOGISCHE HALBLEITERBAUELEMENTE MIT UNTERSCHIEDLICHER ARBEITSFUNKTION AUF EINEM GEMEINSAMEN SUBSTRAT
公开(公告)号：EP3050103A4
公开(公告)日：2017-05-17
申请号：EP13894123
申请日：2013-09-27
申请人： INTEL CORP
发明人： OLAC-VAW ROMAN W , HAFEZ WALID M , JAN CHIA-HONG , LIU PEI-CHI
IPC分类号： H01L21/8234 , H01L21/28 , H01L21/8238 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/66
CPC分类号： H01L21/82345 , H01L21/28088 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L21/823842 , H01L21/845 , H01L23/5283 , H01L27/0886 , H01L27/1211 , H01L29/4966 , H01L29/66545
摘要： Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
摘要翻译：描述了在公共衬底上具有不同功函数的非平面I / O和逻辑半导体器件以及制造在公共衬底上具有不同功函数的非平面I / O和逻辑半导体器件的方法。例如，半导体结构包括设置在衬底上方的第一半导体器件。第一半导体器件具有导电类型并且包括具有第一功函数的栅电极。该半导体结构还包括设置在衬底上方的第二半导体器件。第二半导体器件具有导电类型并且包括具有不同的第二功函数的栅电极。

2. 发明公开

EP2382665A4 FLASH CELL WITH INTEGRATED HIGH-K DIELECTRIC AND METAL-BASED CONTROL GATE 审中-公开
标题翻译：集成高k电介质和金属类的控制栅闪存单元
公开(公告)号：EP2382665A4
公开(公告)日：2014-12-31
申请号：EP09837038
申请日：2009-12-23
申请人： INTEL CORP
发明人： JAN CHIA-HONG , HAFEZ WALID M
IPC分类号： H01L27/115 , H01L21/28 , H01L21/31 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324 , H01L29/7881

3. 发明公开

EP3097580A4 FIN-BASED SEMICONDUCTOR DEVICES AND METHODS 有权
标题翻译： FIN-BASIERTE HALBLEITERBAUELEMENTE UND VERFAHREN
公开(公告)号：EP3097580A4
公开(公告)日：2017-08-16
申请号：EP14879976
申请日：2014-01-24
申请人： INTEL CORP
发明人： HAFEZ WALID M , JAN CHIA-HONG
IPC分类号： H01L21/336 , H01L21/225 , H01L27/02 , H01L29/417 , H01L29/74 , H01L29/78
CPC分类号： H01L29/74 , H01L21/2255 , H01L27/0262 , H01L29/0649 , H01L29/41716 , H01L29/66363 , H01L29/785
摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
摘要翻译：公开了半导体器件，集成电路器件和方法的实施例。在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。第一鳍状物可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，并且第三材料设置在第四材料和第二材料之间。第一和第三材料可以由第一类型的非本征半导体形成，第二和第四材料可以由第二种不同类型的非本征半导体形成。第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一种材料地邻接。其他实施例可以被公开和/或要求保护。

4. 发明公开

EP3182452A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 审中-公开
标题翻译： PRÄZISIONSWIDERSTANDFÜREINE NICHTPLANARE HALBLEITERBAUELEMENTEARCHITEKTUR
公开(公告)号：EP3182452A1
公开(公告)日：2017-06-21
申请号：EP17152588
申请日：2013-06-18
申请人： INTEL CORP
发明人： YEH JENG-YA D , VANDERVOORN PETER J , HAFEZ WALID M , JAN CHIA-HONG , TSAI CURTIS , PARK JOODONG
IPC分类号： H01L27/06 , H01L21/8234 , H01L27/088 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. A semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
摘要翻译：描述了用于非平面半导体器件架构的精密电阻器。半导体结构包括设置在衬底上的第一和第二半导体鳍。隔离区设置在衬底上方，在第一和第二半导体鳍之间，并且高于第一和第二半导体鳍的高度。电阻器结构设置在隔离区上方但不位于第一和第二半导体鳍之上。第一和第二晶体管结构分别由第一和第二半导体鳍形成。

5. 发明公开

EP0803131A4 NOVEL TRANSISTOR WITH ULTRA SHALLOW TIP AND METHOD OF FABRICATION 失效
标题翻译：中性粒细胞EITER ULTRAFLACHEN ZONE UND VERFAHREN ZUR HERSTELLUNG
公开(公告)号：EP0803131A4
公开(公告)日：1998-06-17
申请号：EP95943954
申请日：1995-12-21
申请人： INTEL CORP
发明人： CHAU ROBERT S , CHERN CHAN-HONG , JAN CHIA-HONG , WELDON KEVIN R , PACKAN PAUL A , YAU LEOPOLDO D
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78 , H01L21/44 , H01L21/265 , H01L21/465 , H01L29/04 , H01L29/06 , H01L29/76
CPC分类号： H01L29/66613 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor (200) with a low resistance ultra shallow tip region (214) and its method of fabrication. The novel transistor of the present invention has a source/drain extension of tip region (210) comprising an ultra shallow region (214) which extends beneath the gate electrode and a raised region (216).
摘要翻译：具有低电阻超浅尖端区域（214）的新型晶体管（200）及其制造方法。本发明的新型晶体管具有尖端区域（210）的源极/漏极扩展部分，其包括在栅电极下方延伸的超浅区域（214）和升高区域（216）。

6. 发明公开

EP3161875A4 THROUGH SILICON VIA BASED PHOTOVOLTAIC CELL 审中-公开
公开(公告)号：EP3161875A4
公开(公告)日：2018-02-14
申请号：EP14896213
申请日：2014-06-27
申请人： INTEL CORP
发明人： PHOA KINYIP , NIDHI NIDHI , JAN CHIA-HONG , HAFEZ WALID M , CHEN YI WEI
IPC分类号： H01L31/047 , H01L31/0224 , H01L31/056 , H01L31/068 , H02S40/38
CPC分类号： H01L31/022458 , H01L31/022475 , H01L31/028 , H01L31/047 , H01L31/0516 , H01L31/056 , H01L31/068 , H01L31/0682 , H01L31/1884 , H02S40/38 , Y02E10/52
摘要： An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.

7. 发明公开

EP3087601A4 METAL FUSE BY TOPOLOGY 有权
标题翻译： METALLSICHERUNG NACH TOPOLOGIE
公开(公告)号：EP3087601A4
公开(公告)日：2017-08-16
申请号：EP14873770
申请日：2014-11-26
申请人： INTEL CORP
发明人： LEE CHEN-GUAN , HAFEZ WALID M , JAN CHIA-HONG
IPC分类号： H01L23/60 , H01L23/525 , H01L23/62 , H01L27/04
CPC分类号： H01L23/62 , H01L21/0217 , H01L21/32055 , H01L23/5256 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于集成电路（IC）器件中的过电流熔丝的技术和配置。在一个实施例中，管芯的器件层可以包括第一线结构，该第一线结构具有位于相对的端部之间的凹陷部分以及位于第一线结构的相对侧上的两个第二线结构。隔离材料可以设置在线结构之间的间隙中以及由凹进部分限定的第一凹陷中。隔离材料可以具有限定第一凹陷中的第二凹陷的凹陷部分，并且熔丝结构可以布置在第二凹陷中。其他实施例可以被描述和/或要求保护。

8. 发明公开

EP3061124A4 VERTICAL NON-PLANAR SEMICONDUCTOR DEVICE FOR SYSTEM-ON-CHIP (SOC) APPLICATIONS 审中-公开
标题翻译： VERTIKALES NICHTPLANARES HALBLEITERBAUELEMENTFÜR系统级芯片（SOC）-ANWENDUNGEN
公开(公告)号：EP3061124A4
公开(公告)日：2017-04-26
申请号：EP13894333
申请日：2013-09-26
申请人： INTEL CORP
发明人： JAN CHIA-HONG , HAFEZ WALID M , TSAI CURTIS , YEH JENG-YA D , PARK JOODONG
IPC分类号： H01L21/336 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7851 , H01L27/12 , H01L29/0653 , H01L29/66545 , H01L29/66666 , H01L29/66795 , H01L29/7827 , H01L29/785 , H01L29/78642

9. 发明公开

EP1138075A4 A METHOD AND DEVICE FOR IMPROVED SALICIDE RESISTANCE ON POLYSILICON GATES 有权
标题翻译：方法和元件一起多晶硅栅自调节硅化物提高了抗
公开(公告)号：EP1138075A4
公开(公告)日：2003-05-28
申请号：EP99961599
申请日：1999-11-04
申请人： INTEL CORP
发明人： JAN CHIA-HONG , TSAI JULIE A , YANG SIMON , GHANI TAHIR , WHITEHILL KEVIN A , KEATING STEVEN J , MYERS ALAN
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L29/49 , H01L29/78 , H01L21/8242 , H01L21/3205 , H01L21/8236 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/82345 , H01L29/4933
摘要： A method and device for improved salicide resistance in polysilicon gates under .20 micro meter. The several embodiments of the invention provide for formation of gate electrode structures with recessed and partially recessed spacers. One embodiment, provides a gate electrode structure (220) with recessed thick inner spacers (230) and thick outer spacers (240). Another embodiment provides a gate electrode structure (320) with recessed thin inner spacers (330) and recessed thick outer spacers (340). Another embodiment provides a gate electrode structure (420) with thin inner spacers (430) and partially recessed outer spacers (440). Another embodiment provides a gate electrode structure (520) with two spacer stacks. The outermost spacer stack with recessed thin inner spacers (550) and recessed thick outer spacers (560). The inner spacer stack with thin inner spacers (530) and thin outer spacers (540). Another embodiment provides a gate electrode structure (620) with two spacer stacks. The outermost spacer stack with recessed thin inner spacers (650) and recessed thick outer spacers (660). The inner spacer stack with recessed thin inner spacers (630) and recessed thin outer spacers (640).
摘要翻译：一种用于在多晶硅栅自对准硅化物的改进阻力下0.20微米的方法和装置。在本发明的几个实施例提供了具有凹陷和凹进部分形成间隔物栅极电极结构。一个实施例中，可以获取与凹厚内侧间隔片（230）和厚外隔离件（240）的栅极电极结构（220）。另一个实施方案提供用凹薄内侧间隔片（330）和凹进厚外隔离件（340）的栅极电极结构（320）。另一个实施方案提供具有薄内侧间隔片（430）和部分地凹入外隔离件（440）的栅极电极结构（420）。另一实施例提供了两个间隔堆叠的栅极电极结构（520）。与凹薄内侧间隔片（550）和凹进厚外隔离件（560）最外部隔离物堆叠。薄内分隔件（530）和薄的外间隔件（540）的内隔离物堆叠。另一实施例提供了两个间隔堆叠的栅极电极结构（620）。与凹薄内侧间隔片（650）和凹进厚外隔离件（660）最外部隔离物堆叠。与凹薄内侧间隔片（630）和凹进薄外隔离件（640）的内隔离物堆叠。

10. 发明公开

EP0853815A4 FORMATION OF SOURCE/DRAIN FROM DOPED GLASS 失效
标题翻译：源极/漏极与玻璃CLOTIERTEM的形成
公开(公告)号：EP0853815A4
公开(公告)日：1999-10-27
申请号：EP96934065
申请日：1996-10-03
申请人： INTEL CORP
发明人： THOMPSON SCOTT E , JAN CHIA-HONG , PACKAN PAUL A , GHANI TAHIR , ANDIDEH EBRAHIM , MOGHADAM FARHAD K , BOHR MARK T
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78 , H01L21/385 , H01L21/8232
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/823814 , H01L29/6656
摘要： A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer (16) of glass (2 % BSG) is used to provide the source of doping for the tip region and a second layer (35) of glass (6 % BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers (31) are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

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