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1. 发明授权

EP3035387B1 NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 有权转让
标题翻译：具有多电介质栅堆叠的III-V族材料有源区的非平面半导体器件
公开(公告)号：EP3035387B1
公开(公告)日：2018-05-16
申请号：EP16153103.3
申请日：2013-06-12
申请人： Intel Corporation
发明人： Dewey, Gilbert , Radosavljevic, Marko , Pillarisetty, Ravi , Chu-Kung, Bejamin , Mukherjee, Niloy
IPC分类号： H01L29/06 , H01L29/775 , H01L29/423 , H01L29/78 , H01L29/786 , H01L29/205
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body (206) with a channel region. A source and drain material region (226) is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack (220, 222, 224) is disposed in the trench and on the exposed portion of the channel region. The gate stack includes a first dielectric layer (220) on outer portions of the channel region (206), a second dielectric layer (222) on an inner portion of the channel region, and a gate electrode (224).

2. 发明授权

EP2638565B1 A METHOD FOR TREATING A SUBSTRATE AND A SUBSTRATE 有权转让
标题翻译：一种处理基板和基板的方法
公开(公告)号：EP2638565B1
公开(公告)日：2018-05-16
申请号：EP11791014.1
申请日：2011-11-08
申请人： Comptek Solutions Oy
发明人： LANG, Jouko , PUNKKINEN, Marko , TUOMINEN, Marjukka , TUOMINEN, Veikko , DAHL, Johnny , VÄYRYNEN, Juhani , LAUKKANEN, Pekka
IPC分类号： H01L21/316 , H01L21/02 , H01L21/28 , H01L29/20
CPC分类号： H01L29/02 , H01L21/02046 , H01L21/02109 , H01L21/02172 , H01L21/02241 , H01L21/28264 , H01L21/31666 , H01L21/3245 , H01L29/1054 , H01L29/20 , H01L29/201 , H01L29/205
摘要： A method for treating a compound semiconductor substrate, in which method in vacuum conditions a surface of an In-containing III-As, III-Sb or III-P substrate is cleaned from amorphous native oxides and after that the cleaned substrate is heated to a temperature of about 250-550° C. and oxidized by introducing oxygen gas onto the surface of the substrate. The invention relates also to a compound semiconductor substrate, and the use of the substrate in a structure of a transistor such as MOSFET.

3. 发明公开

EP3050115A4 VERTICAL TRANSISTOR DEVICES FOR EMBEDDED MEMORY AND LOGIC TECHNOLOGIES 审中-公开
标题翻译： VERTIKALE TRANSISTORVORRICHTUNGENFÜREINGEBETTETEN SPEICHER UND LOGISCHE TECHNOLOGIEN
公开(公告)号：EP3050115A4
公开(公告)日：2017-08-30
申请号：EP14846896
申请日：2014-09-02
申请人： INTEL CORP
发明人： DOYLE BRIAN S , SHAH UDAY , KOTLYAR ROZA , KUO CHARLES C
IPC分类号： H01L21/336 , H01L29/10 , H01L29/161 , H01L29/165 , H01L29/78
CPC分类号： H01L29/66666 , H01L21/02532 , H01L21/30604 , H01L29/0847 , H01L29/1037 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/201 , H01L29/205 , H01L29/4983 , H01L29/66356 , H01L29/66363 , H01L29/7391 , H01L29/749 , H01L29/7827 , H01L29/7848
摘要： Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.
摘要翻译：描述了垂直晶体管器件。例如，在一个实施例中，垂直晶体管器件包括设置在衬底上的外延源半导体区，设置在源半导体区上的外延沟道半导体区，设置在沟道半导体区上的外延漏半导体区以及栅电极区域围绕半导体沟道区域的侧壁。至少一个半导体区域的成分沿着垂直于衬底表面的纵向轴线变化。

4. 发明公开

EP2901485A4 NON-PLANAR SEMICONDUCTOR DEVICE HAVING GROUP III-V MATERIAL ACTIVE REGION WITH MULTI-DIELECTRIC GATE STACK 有权转让
标题翻译：具有多电介质堆栈III-V族材料的有源区域的非平面半导体元件
公开(公告)号：EP2901485A4
公开(公告)日：2016-06-01
申请号：EP13840258
申请日：2013-06-12
申请人： INTEL CORP
发明人： DEWEY GILBERT , RADOSAVLJEVIC MARKO , PILLARISETTY RAVI , CHU-KUNG BENJAMIN , MUKHERJEE NILOY
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/51 , H01L29/775
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y99/00 , H01L29/0665 , H01L29/201 , H01L29/205 , H01L29/408 , H01L29/4236 , H01L29/42364 , H01L29/42392 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/78696
摘要： Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body (206) with a channel region. A source and drain material region (226) is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack (220, 222, 224) is disposed in the trench and on the exposed portion of the channel region. The gate stack includes a first dielectric layer (220) on outer portions of the channel region (206), a second dielectric layer (222) on an inner portion of the channel region, and a gate electrode (224).

5. 发明公开

EP3012868A1 TECHNIQUES FOR FORMING CONTACTS TO QUANTUM WELL TRANSISTORS 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG VON KONTAKTENFÜRQUANTENTROG-TRANSISTOREN
公开(公告)号：EP3012868A1
公开(公告)日：2016-04-27
申请号：EP15196597.7
申请日：2010-12-02
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , KAVALIEROS, Jack, T. , CHU-KUNG, Benjamin , RACHMADY, Willy , HUDAIT, Mantu, K. , MUKHERJEE, Niloy , RADOSAVLJEVIC, Marko , CHAU, Robert, S.
IPC分类号： H01L29/778 , H01L21/336 , H01L29/417 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7784 , H01L29/151 , H01L29/155 , H01L29/201 , H01L29/205 , H01L29/401 , H01L29/41725 , H01L29/41775 , H01L29/42316 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/775 , H01L29/7783 , H01L29/78
摘要： Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
摘要翻译：公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。这些技术可以用于例如形成与在III-V和SiGe / Ge材料体系中制造的量子阱晶体管的栅极，源极和漏极区的接触。不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离通过间隔材料。

6. 发明公开

EP2913853A2 Semiconductor device 审中-公开
标题翻译： Halbleiterbauelement
公开(公告)号：EP2913853A2
公开(公告)日：2015-09-02
申请号：EP15150397.6
申请日：2015-01-08
申请人： Renesas Electronics Corporation
发明人： Miura, Yoshinao , Nakayama, Tatsuo , Inoue, Takashi , Miyamoto, Hironobu
IPC分类号： H01L29/778 , H01L21/336 , H01L29/417 , H01L29/10 , H01L29/423 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/1087 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66462 , H01L29/7783
摘要： The semiconductor device has, over a substrate (S) thereof, a first buffer layer (GaN) (BU1), a second buffer layer (AlGaN) (BU2), a channel layer (CH), and a barrier layer (BA), a trench (T) penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode (GE) placed in the trench via a gate insulating film (GI), and a source electrode (SE) and a drain electrode (DE) formed on respective sides of the gate electrode. By a coupling portion (VIA) in a through-hole (TH) reaching the first buffer layer, the first buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas (2DEG2) produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.
摘要翻译：半导体器件在其衬底（S）上具有第一缓冲层（GaN）（BU1），第二缓冲层（AlGaN）（BU2），沟道层（CH）和势垒层（BA）穿过阻挡层并到达沟道层中间的沟槽（T），通过栅极绝缘膜（GI）放置在沟槽中的栅电极（GE），以及源极（SE）和漏电极（ DE）形成在栅电极的相应侧上。通过到达第一缓冲层的通孔（TH）中的耦合部分（VIA），第一缓冲层和源电极彼此电耦合。由于在这两个缓冲层之间的界面附近产生的二维电子气（2DEG2），所以半导体器件可以具有增加的阈值电压和改善的常关特性。

7. 发明公开

EP2897157A1 Nitride semiconductor element and nitride semiconductor wafer 审中-公开
标题翻译： Nitrid-Halbleiterement和Nitrid-Halbleiterwafer
公开(公告)号：EP2897157A1
公开(公告)日：2015-07-22
申请号：EP14200332.6
申请日：2014-12-24
申请人： Kabushiki Kaisha Toshiba
发明人： Hikosaka, Toshiki , Yoshida, Hisashi , Nago, Hajime , Nunoue, Shinya
IPC分类号： H01L21/02
CPC分类号： H01L29/201 , H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/02505 , H01L21/0254 , H01L21/02584 , H01L21/0262 , H01L29/1075 , H01L29/2003 , H01L29/205 , H01L29/267 , H01L29/365 , H01L29/778 , H01L29/78 , H01L29/872 , H01L33/0025 , H01L33/025 , H01L33/32
摘要： According to one embodiment, a nitride semiconductor element (110, 120, 121, 125, 150, 160) includes a functional layer (10) and a stacked body (50). The stacked body (50) includes a GaN intermediate layer (51, 51a, 51b), a low Al composition layer (54, 54a, 54b), a high Al composition layer (53, 53a, 53b), and a first Si-containing layer (52, 52a, 52b). The low Al composition layer (54, 54a, 54b) includes a nitride semiconductor having a first Al composition ratio. The low Al composition layer (54, 54a, 54b) is provided between the GaN intermediate layer (51, 51a, 51b) and the functional layer (10). The high Al composition layer (53, 53a, 53b) includes a nitride semiconductor having a second Al composition ratio. The high Al composition layer (53, 53a, 53b) is provided between the GaN intermediate layer (51, 51a, 51b) and the low Al composition layer (54, 54a, 54b). The second Al composition ratio is higher than the first Al composition ratio. The first Si-containing layer (52, 52a, 52b) is provided between the GaN intermediate layer (51, 51a, 51b) and the high Al composition layer (53, 53a, 53b).
摘要翻译：根据一个实施例，氮化物半导体元件（110,120,121,125,150,160）包括功能层（10）和层叠体（50）。层叠体（50）包括GaN中间层（51,51a，51b），低Al组成层（54,54a，54b），高Al组成层（53,53a，53b）和第一Si- （52,52a，52b）。低Al组分层（54,54a，54b）包括具有第一Al组成比的氮化物半导体。低铝组成层（54,54a，54b）设置在GaN中间层（51,51a，51b）和功能层（10）之间。高Al组分层（53,53a，53b）包括具有第二Al组成比的氮化物半导体。高Al组分层（53,53a，53b）设置在GaN中间层（51,51a，51b）和低Al组成层（54,54a，54b）之间。第二Al组成比高于第一Al组成比。第一含硅层（52,52a，52b）设置在GaN中间层（51,51a，51b）和高Al组成层（53,53a，53b）之间。

8. 发明授权

EP2131398B1 COMPOUND SEMICONDUCTOR LAMINATE, PROCESS FOR PRODUCING THE COMPOUND SEMICONDUCTOR LAMINATE, AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体复合层压板，一种用于制造半导体层积体和半导体器件
公开(公告)号：EP2131398B1
公开(公告)日：2015-05-20
申请号：EP08738698.3
申请日：2008-03-21
申请人： Asahi Kasei EMD Corporation
发明人： SHIBATA, Yoshihiko , MIYAHARA, Masatoshi
IPC分类号： H01L29/26 , C30B23/02 , C30B29/40 , C30B25/18 , H01L21/20 , H01L29/20 , H01L43/06 , H01L43/08
CPC分类号： H01L29/20 , C30B23/025 , C30B25/18 , C30B29/40 , C30B29/406 , H01L21/02381 , H01L21/02439 , H01L21/0254 , H01L21/02549 , H01L29/201 , H01L29/267 , H01L43/065

9. 发明公开

EP2869347A1 Group III-V device including a buffer termination body 审中-公开
标题翻译： Gruppe-III-V-Bauelement mitPufferabschlusskörper
公开(公告)号：EP2869347A1
公开(公告)日：2015-05-06
申请号：EP14189359.4
申请日：2014-10-17
申请人： International Rectifier Corporation
发明人： Briere, Michael A.
IPC分类号： H01L29/778 , H01L21/338 , H01L29/205 , H01L29/20 , H01L29/201
CPC分类号： H01L29/778 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/66431 , H01L29/66462 , H01L29/7783
摘要： A III-Nitride device includes a III-Nitride buffer layer (332) situated over a substrate (310), the III-Nitride buffer layer having a first bandgap. In addition, the device includes a III-Nitride heterostructure situated over the III-Nitride buffer layer and configured to produce a two-dimensional electron gas (2DEG) (355); the III-Nitride heterostructure includes a channel layer (354) having a second bandgap smaller than the first bandgap. The III-Nitride device also includes a buffer termination body (342) situated between the III-Nitride buffer layer and the channel layer, the buffer termination body including a III-Nitride material having a third bandgap smaller than the first bandgap and larger the second bandgap.
摘要翻译： III-氮化物器件包括位于衬底（310）上方的III-氮化物缓冲层（332），所述III-氮化物缓冲层具有第一带隙。此外，该器件包括位于III-氮化物缓冲层之上并被配置为产生二维电子气（2DEG）（355）的III-氮化物异质结构。 III-氮化物异质结构包括具有小于第一带隙的第二带隙的沟道层（354）。 III-氮化物装置还包括位于III-氮化物缓冲层和沟道层之间的缓冲端接体（342），缓冲端接体包括具有小于第一带隙的第三带隙的III-氮化物材料，并且第二带隙。

10. 发明公开

EP2711975A1 SEMICONDUCTOR ELEMENT AND METHOD FOR PRODUCING SAME 审中-公开
标题翻译：半导体元件及其制造方法
公开(公告)号：EP2711975A1
公开(公告)日：2014-03-26
申请号：EP12784883.6
申请日：2012-05-10
申请人： Advanced Power Device Research Association
发明人： KOKAWA, Takuya , KATOU, Sadahiro , IWAMI, Masayuki , UTSUMI, Makoto , UMENO, Kazuyuki
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/2003 , H01L21/02389 , H01L21/02433 , H01L21/02458 , H01L21/02507 , H01L21/0251 , H01L21/0254 , H01L21/02576 , H01L21/02579 , H01L21/02581 , H01L21/0262 , H01L29/1075 , H01L29/201 , H01L29/7787
摘要： Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer. The buffer region includes a plurality of semiconductor layers having different lattice constants, and there is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when a potential that is less than a potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region.
摘要翻译：本发明提供泄漏电流小的氮化物系半导体元件及其制造方法。该半导体元件包括衬底; 缓冲区域，形成在所述基板上方; 形成在缓冲区上的有源层; 以及形成在有源层上的至少两个电极。缓冲区包括具有不同晶格常数的多个半导体层，并且当电势低于底表面的电势时，在衬底的底表面和缓冲区的顶表面之间存在基本恒定的静电电容的衬底施加到缓冲区的顶表面并且衬底的底表面和缓冲区的顶表面之间的电压在对应于缓冲区的厚度的范围内改变。

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