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1. 发明公开

EP3474316A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3474316A1
公开(公告)日：2019-04-24
申请号：EP16910453.6
申请日：2016-07-25
申请人： Mitsubishi Electric Corporation
发明人： YAMAGUCHI, Yutaro , HANGAI, Masatake , YAMANAKA, Koji
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
摘要： A semiconductor device (1) includes: an underlying substrate; a semiconductor layer formed on the underlying substrate; electrode patterns (10 and 21 to 24) in which a drain electrode and a source electrode are alternately arranged along an array direction (X) determined in advance, on the semiconductor layer; and a group of gate fingers (31 to 38) each having a shape extending in an extending direction (Y) which is different from the array direction (X). Each of the gate fingers (31 to 38) is disposed in a region between the drain electrode and the source electrode. Moreover, the gate fingers (31 to 38) are arranged at positions displaced from one another in the extending direction (Y).

2. 发明公开

EP3373455A1 HIGH FREQUENCY SWITCH 有权
公开(公告)号：EP3373455A1
公开(公告)日：2018-09-12
申请号：EP15910218.5
申请日：2015-12-09
申请人： Mitsubishi Electric Corporation
发明人： KOMARU, Ryota , HANGAI, Masatake , YAMANAKA, Koji
IPC分类号： H04B1/44
CPC分类号： H01P1/15 , H03K17/693 , H04B1/48
摘要： There are provided: a first capacitor connected between first and second input/output terminals; a second capacitor connected between the first input/output terminal and a third input/output terminal; a first inductor having one end connected to the first input/output terminal; a second inductor having one end connected to the second input/output terminal and another end connected to another end of the first inductor; a third inductor having one end connected to the first input/output terminal; a fourth inductor having one end connected to the third input/output terminal and another end connected to another end of the third inductor; a first transistor having a drain terminal connected to said another ends of the first and second inductors and a source terminal that is grounded; and a second transistor having a drain terminal connected to said another ends of the third and fourth inductors and a source terminal that is grounded.

3. 发明公开

EP3700087A1 DOHERTY AMPLIFIER AND DOHERTY AMPLIFIER CIRCUIT 有权
公开(公告)号：EP3700087A1
公开(公告)日：2020-08-26
申请号：EP17932410.8
申请日：2017-11-15
申请人： Mitsubishi Electric Corporation
发明人： NAKATANI, Keigo , KOMATSUZAKI, Yuji , SAKATA, Shuichi , SHINJO, Shintaro , YAMANAKA, Koji
IPC分类号： H03F1/07 , H03F3/68
摘要： Included is a compensation circuit (9) having one end connected to another end of a first output circuit (7) and another end of a second output circuit (8) and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

4. 发明公开

EP3648343A1 DOHERTY AMPLIFIER AND AMPLIFICATION CIRCUIT 有权
公开(公告)号：EP3648343A1
公开(公告)日：2020-05-06
申请号：EP17919295.0
申请日：2017-07-27
申请人： Mitsubishi Electric Corporation
发明人： NAKATANI, Keigo , SAKATA, Shuichi , SHINJO, Shintaro , YAMANAKA, Koji
IPC分类号： H03F1/07
摘要： In a case where the power of a signal to be amplified is greater than or equal to a threshold value, a signal distributor (2) outputs one of signals to a carrier amplifier (6), outputs another signal, a phase of which is 90 degrees behind that of the one of the signals, to a peak amplifier (8), and adjusts a phase shift amount of a signal shifted by a phase shifter (7) depending on the frequency of the signal to be amplified. In a case where the power of the signal to be amplified is less than the threshold value, the signal distributor (2) outputs the one of the signals to the carrier amplifier (6) without outputting the other signal to the peak amplifier (8).

5. 发明公开

EP3460902A1 HIGH FREQUENCY SWITCH 审中-公开
公开(公告)号：EP3460902A1
公开(公告)日：2019-03-27
申请号：EP16907240.2
申请日：2016-06-28
申请人： Mitsubishi Electric Corporation
发明人： KOMARU, Ryota , HANGAI, Masatake , YAMANAKA, Koji , SUGIMOTO, Atsuo
IPC分类号： H01P1/15
摘要： A second transistor (2b), which is turned on when a first transistor (2a) is turned off, is shunt-connected between a first transmission line (3a) and a second transmission line (3b). A fourth transistor (2d), which is turned off when a third transistor (2c) is turned on, is shunt-connected between a third transmission line (3c) and a fourth transmission line (3d). Each of a common terminal transmission line (3e), the first and second transmission lines (3a and 3b), and the third and fourth transmission lines (3c and 3d) is set to have an electrical length of a quarter wavelength at the center frequency of an input signal. The first transistor (2a) and the third transistor (2c) are complementary turned on and off, and characteristic impedances of the common terminal transmission line (3e), the first transmission line (3a), and the third transmission line (3c) are set to be lower than those of peripheral circuits.

6. 发明公开

EP2639820A1 SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE 审中-公开
标题翻译： HERBLEITERBAUEMENT UND HERSTELLUNGSVERFAHRENFÜRDAS HALBLEITERBAUELEMENT
公开(公告)号：EP2639820A1
公开(公告)日：2013-09-18
申请号：EP10859611.5
申请日：2010-11-10
申请人： Mitsubishi Electric Corporation
发明人： OISHI, Toshiyuki , OTSUKA, Hiroshi , YAMANAKA, Koji , YAMAUCHI, Kazuhisa , HANGAI, Masatake , NAKAYAMA, Masatoshi
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
CPC分类号： H01L29/2003 , H01L21/0254 , H01L29/0607 , H01L29/0657 , H01L29/205 , H01L29/7786
摘要： It is an object to attain both high gain and a broad band (that is, to attain both reduction in a gate-drain capacitance and reduction in a source-drain capacitance). Provided is a semiconductor device, including: a GaN channel layer (3) through which electrons travel; a barrier layer (4) which is provided on the GaN channel layer in order to form two-dimensional electron gas in the GaN channel layer and which contains at least any one of In, Al, and Ga and contains N; a gate electrode (8), a source electrode (6), and a drain electrode (7); and a plate (20) formed of a material having polarization, which is provided between the gate electrode (8) and the drain electrode (7), the plate being held in contact with a part of the barrier layer (4).
摘要翻译：其目的在于获得高增益和宽带（即，获得栅极 - 漏极电容的减小和源极 - 漏极电容的降低）。提供一种半导体器件，包括：电子行进的GaN沟道层（3）; 阻挡层（4），其设置在所述GaN沟道层上，以在所述GaN沟道层中形成二维电子气，并且其包含In，Al和Ga中的至少任一个并且包含N; 栅电极（8），源电极（6）和漏电极（7）; 以及设置在所述栅极（8）和所述漏电极（7）之间的具有偏振材料的板（20），所述板与所述阻挡层（4）的一部分保持接触。

7. 发明公开

EP4307561A1 DOHERTY AMPLIFIER 审中-实审
公开(公告)号：EP4307561A1
公开(公告)日：2024-01-17
申请号：EP21936993.1
申请日：2021-04-16
申请人： MITSUBISHI ELECTRIC CORPORATION
发明人： KOMATSUZAKI, Yuji , SAKATA, Shuichi , YAMANAKA, Koji
IPC分类号： H03F1/02 , H03F1/07 , H03F3/68
摘要： A Doherty amplifier includes: a first filter circuit (6a) to, when receiving an input signal lying in a first frequency band, output a first input signal obtained by attenuating the input signal by a first amount of attenuation, and to, when receiving an input signal lying in a second frequency band different from the first frequency band, output a second input signal obtained by allowing passage of the input signal; a second filter circuit (6b) to, when receiving an input signal lying in the first frequency band, output a third input signal obtained by attenuating the input signal by a second amount of attenuation smaller than the first amount of attenuation, and to, when receiving an input signal lying in the second frequency band, output a fourth input signal obtained by attenuating the input signal by a third amount of attenuation larger than or equal to the first amount of attenuation; a first amplifier (8a) in which a gate bias voltage is fixed, the first amplifier (8a) being configured to operate as an auxiliary amplifier when receiving the first input signal from the first filter circuit (6a), and to operate as a main amplifier when receiving the second input signal from the first filter circuit (6a); and a second amplifier (8b) in which a gate bias voltage is fixed, the second amplifier (8b) being configured to operate as the main amplifier when receiving the third input signal from the second filter circuit (6b), and to operate as the auxiliary amplifier when receiving the fourth input signal from the second filter circuit (6b).

8. 发明公开

EP3780390A1 DISTRIBUTED AMPLIFIER 有权
公开(公告)号：EP3780390A1
公开(公告)日：2021-02-17
申请号：EP18917811.4
申请日：2018-05-09
申请人： Mitsubishi Electric Corporation
发明人： KAMIOKA, Jun , HANGAI, Masatake , YAMANAKA, Koji
IPC分类号： H03F3/68 , H03F3/60
摘要： CRLH lines (10a to 10d) including left-handed shunt inductors (7a to 7d) and left-handed series capacitors (6a to 6d) are provided on gate side transmission lines (4a to 4d) of a plurality of FETs (3a to 3d).

9. 发明公开

EP3770954A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：EP3770954A1
公开(公告)日：2021-01-27
申请号：EP18920641.0
申请日：2018-06-01
申请人： Mitsubishi Electric Corporation
发明人： YAMAGUCHI, Yutaro , HANGAI, Masatake , SHINJO, Shintaro , YAMANAKA, Koji
IPC分类号： H01L21/8232 , H01L21/338 , H01L27/06 , H01L29/812
摘要： In a semiconductor device (1) including gate fingers (2a to 2h) each having a linear shape extending from a feed line (6), and arranged in areas between drain electrodes (3a to 3e) and source electrodes (4a to 4d), open stubs (8a to 8h) are connected directly to the feed line (6).

10. 发明公开

EP3462608A1 AMPLIFIER 审中-公开
公开(公告)号：EP3462608A1
公开(公告)日：2019-04-03
申请号：EP16907344.2
申请日：2016-07-01
申请人： Mitsubishi Electric Corporation
发明人： NAKATANI, Keigo , KOMATSUZAKI, Yuji , SHINJO, Shintaro , YAMANAKA, Koji , IMAI, Shohei
IPC分类号： H03F1/08 , H03F1/42
摘要： Parallel inductors include a first metal wire (8a or 8b) for connecting a drain terminal (2) and a first metal pattern (7a or 7b), and a second metal wire (10a or 10b) for connecting the first metal pattern (7a or 7b) and a second metal pattern (9a or 9b). The second metal wires (10a and 10b) are each positioned between the corresponding first metal wire (8a or 8b) and a corresponding third metal wire (12a or 12b) for connecting the drain terminal (2) and a third metal pattern (11). The direction of current through the second metal wires (10a and 10b) is opposite to the direction of current through each of the first metal wire (8a or 8b) and the third metal wire (12a or 12b).

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