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1. 发明授权

EP2232493B1 METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM 有权转让
标题翻译：用于校准存储器系统中的写时序的方法和设备
公开(公告)号：EP2232493B1
公开(公告)日：2018-05-09
申请号：EP08731251.8
申请日：2008-03-03
申请人： Rambus Inc.
发明人： GIOVANNINI, Thomas , GUPTA, Alok , SHAEFFER, Ian , WOO, Steven C.
IPC分类号： G11C11/4076 , G11C7/10 , G11C11/409 , G11C11/4096 , G06F3/06 , G06F1/08 , G06F5/06
CPC分类号： G11C11/4076 , G06F1/08 , G06F3/0629 , G06F3/0634 , G06F5/06 , G06F12/0646 , G06F13/1689 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/409 , G11C11/4096 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

2. 发明公开

EP3186831A1 SILICON GERMANIUM READ PORT FOR A STATIC RANDOM ACCESS MEMORY REGISTER FILE 审中-公开
标题翻译：硅锗读取端口为静态随机访问存储器寄存器文件
公开(公告)号：EP3186831A1
公开(公告)日：2017-07-05
申请号：EP15745707.8
申请日：2015-07-23
申请人： Qualcomm Incorporated
发明人： MOJUMDER, Niladri , SONG, Stanley Seungchul , WANG, Zhongze , YEAP, Choh Fei
IPC分类号： H01L27/11 , H01L29/10 , G11C11/412
CPC分类号： G11C11/419 , G11C11/405 , G11C11/409 , G11C11/412 , H01L27/1104 , H01L27/1116 , H01L29/1054
摘要： A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.
摘要翻译：静态随机存取存储器（SRAM）电路包括写入端口和耦合到写入端口的读取端口。读取端口包括读取位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。读取端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

3. 发明公开

EP2849075A8 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
公开(公告)号：EP2849075A8
公开(公告)日：2015-09-16
申请号：EP14196752.1
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

4. 发明公开

EP2273376A1 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP2273376A1
公开(公告)日：2011-01-12
申请号：EP10179110.1
申请日：2002-04-23
申请人： Rambus Inc.
发明人： Ware, Frederick , Tsern,, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/16
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.

5. 发明公开

EP1653374A2 Method and apparatus for coordinating memory operations among diversely-located memory components 有权
标题翻译：用于协调不同布置的存储元件之间的存储器操作的方法和装置
公开(公告)号：EP1653374A2
公开(公告)日：2006-05-03
申请号：EP05022021.9
申请日：2002-04-23
申请人： Rambus, Inc.
发明人： Ware, Frederick A. , Tsern, Ely K. , Perego, Richard E. , Hampel, Craig E.
IPC分类号： G06F13/42
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method and apparatus for coordinating memory operations among diversely-located memory components is described. In accordance with an embodiment of the invention, wave-pipelining is implemented for an address bus coupled, to a plurality of memory components. The plurality of memory components are configured according to coordinates relating to the address bus propagation delay and the data bus propagation delay. A timing signal associated with address and/or control signals which duplicates the propagation delay of these signals is used to coordinate memory operations.
摘要翻译：一种用于多样-位于存储器组件之间进行协调的存储器操作的方法和装置进行说明。在与本发明的实施方式雅舞蹈，波浪流水线被实现为与地址总线耦合到存储器元件的复数。存储器组件的多元性是被配置gemäß到坐标与地址总线传播延迟和数据总线传播延迟。哪个复制合成信号的传播延迟与地址和/或控制信号相关联的定时信号用于协调存储器操作。

6. 发明公开

EP1220226A2 Multi-port memory based on DRAM core 有权
公开(公告)号：EP1220226A2
公开(公告)日：2002-07-03
申请号：EP01308424.9
申请日：2001-10-02
申请人： FUJITSU LIMITED
发明人： Matsuzaki, Yasurou, c/o Fujitsu Limited , Suzuki, Takaaki, c/o Fujitsu Limited , Yamazaki, Masafumi, c/o Fujitsu Limited , Kawasaki, Kenichi, c/o Fujitsu Limited , Kamata, Shinnosuke, c/o Fujitsu Limited
IPC分类号： G11C8/16
CPC分类号： G11C7/1051 , G11C7/1039 , G11C7/1075 , G11C7/1078 , G11C7/22 , G11C8/16 , G11C11/406 , G11C11/40603 , G11C11/40615 , G11C11/40618 , G11C11/409 , G11C2207/107
摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

7. 发明公开

EP0398244A2 Dynamic type random-acces memory 失效
标题翻译： om chen chen chen
公开(公告)号：EP0398244A2
公开(公告)日：1990-11-22
申请号：EP90109122.3
申请日：1990-05-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Ohsawa, Takashi, c/o Intellectual Property Div.
IPC分类号： G11C11/407 , G11C11/409
CPC分类号： G11C11/4096 , G11C11/409 , G11C11/4091
摘要： This invention discloses a dynamic type random-access memory which includes a bit line pair, a memory cell array including a plurality of memory cells (MC i ; i = 0 to 255), a bit line sense amplifier (NA, PA) which is enabled after data written in one of the plurality of memory cells (MC i ; i = 0 to 255) is read out onto the bit line pair, and a charge transfer circuit (NT₁, NT₂) which is connected between the bit line pair and sense nodes (SN, SN ) of the bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of the bit line sense amplifier (NA, PA) is started.
摘要翻译：本发明公开了一种动态型随机存取存储器，它包括位线对，包括多个存储单元（MCi; i = 0至255）的存储单元阵列，使能的位线读出放大器（NA，PA）在将多个存储单元（MCi; i = 0〜255）中的一个写入的数据被读出到位线对上之后，连接在位线对和感测节点之间的电荷转移电路（NT1，NT2）（NA，PA）的位线读出放大器（NA，PA）的检测放大（SN，SN）之后，在位线读出放大器（NA，PA）的读出放大动作开始后，保持关闭一段规定的时间。

8. 发明公开

EP0280882A2 Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time 失效
标题翻译：组织的块RAM内存，能够存储数据的读取，写入和块访问时间劲达。
公开(公告)号：EP0280882A2
公开(公告)日：1988-09-07
申请号：EP88101323.9
申请日：1988-01-29
申请人： RCA Thomson Licensing Corporation
发明人： Todd, Christopher J.
IPC分类号： G11C8/00 , G11C7/00 , G11C11/406 , G11C11/407
CPC分类号： H04N5/907 , G11C7/22 , G11C8/12 , G11C11/406 , G11C11/4076 , G11C11/409
摘要： A video memory system which uses dynamic digital data storage elements allows random access to blocks of 32 pixel values. The pixel values to be stored in a block (50) are applied sequentially to the memory system and the pixel values provided by the memory system are provided sequentially. The block oriented random access memory which stores and provides the blocks of 32 pixel values is configured (22,30,31,34,36) to be able to perform a block read, a block write and a refresh operation in the time (T WR + T RD + T RE ) required to provide one 32 pixel block to or from the video memory system.
摘要翻译：其中采用动态数字数据存储元件的视频存储器系统允许32个象素值的块的随机访问。的像素值要被存储在一个块（50）被施加到按顺序由存储器系统所提供的存储器系统以及像素值被依次设置。存储并提供32个的像素值的块的面向块的随机存取存储器被配置（22,30,31,34,36），以能够在时间执行块的读取，BlockWrite命令和刷新手术（TWR + TRD + TRE）要求提供一个32像素块或从视频存储器系统。

9. 发明公开

EP0209050A2 Semiconductor memory capable of executing logical operation 失效
标题翻译：半导体存储器，能够执行的逻辑操作的。
公开(公告)号：EP0209050A2
公开(公告)日：1987-01-21
申请号：EP86109292.2
申请日：1986-07-08
申请人： NEC CORPORATION
发明人： Imazeki, Shuichi , Ikeda, Hiroaki
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： H03K19/1776 , G11C7/1006 , G11C11/409 , G11C11/4096 , G11C11/4099 , H03K19/094 , H03K19/17728 , H03K19/17792
摘要： A semiconductor memory is capable of executing a logical operation, which comprises at least one sense amplifier having a pair of inputs connected to a pair of bit lines; and a pair of output lines connected to the pair of bit lines, respectively. At least a pair of memory cells and a pair of dummy cells are connected to the pair of bit lines, respectively. Further, at least a pair of word lines are connected to the pair of memory cells, respectively, and a pair of dummy word lines connected to the pair of dummy cells, respectively. A word selecting circuit is connected to the pair of word lines and is capable of activating the pair of word lines at the same time. In addition, a dummy cell selecting circuit is connected to the pair of dummy word lines and adapted to alternatively activate the pair of dummy cells. A controller is provided for controlling the word selecting circuit and the dummy cell selecting circuit so that the sense amplifier is activated after the pair of word lines is activated by the word selecting circuit and a selected one of the dummy cells is activated by the dummy cell selecting circuit. As a result, the result of an logical operation on two bits of data respectively read from the pair of memory cells will outputted on the pair of data lines.

10. 发明公开

EP0172112A2 Semiconductor memory device 失效
公开(公告)号：EP0172112A2
公开(公告)日：1986-02-19
申请号：EP85401626.8
申请日：1985-08-09
申请人： FUJITSU LIMITED
发明人： Baba, Fumio , Takemae, Yoshihiro
IPC分类号： G11C7/00 , G11C11/24
CPC分类号： G11C7/00 , G11C7/20 , G11C11/409 , G11C11/4094 , G11C11/4096
摘要： A semiconductor memory device having a data inverting circuit (Qa, Qb, Qc, Qd) for selectively inverting an input/ output data (Din, Dout) of a sense amplifier (SA 1 , SA 2 , ...) in such a way that the charging states of respective memory cells (MC 1,1 ,...,MC 2,1 ,...) connected to the two bit lines (BI 1 , BI 2 ,...) in each bit line pair become equal for the same input/output data, and a clamp circuit (Q 13 , Q 14 , Q 23 ,...) for drawing the potentials of all of the bit lines to a predetermined potential in response to a clear control signal (CLR), whereby the contents of all of the memory cells can be cleared at the same time.

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