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1. 发明授权

EP1387256B1 Program counter adjustment based on the detection of an instruction prefix 有权
公开(公告)号：EP1387256B1
公开(公告)日：2018-11-21
申请号：EP03291920.1
申请日：2003-07-30
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gérard , Lassère, Serge , Kuusela, Maija
IPC分类号： G06F9/318 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/30076 , G06F9/30181 , G06F9/30185 , G06F9/382 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecodes in parallel with the decoder decoding a current instruction. The pre-decoder determines if a subsequent instruction contains a prefix. If a prefix is detected in at least one of the five Bytecodes, a program counter skips the prefix and changes the behavior of the decoder during the decoding of the subsequent instruction.

2. 发明授权

EP2843551B1 Multi-core synchronization mechanism 有权
公开(公告)号：EP2843551B1
公开(公告)日：2018-09-19
申请号：EP14179296.0
申请日：2014-07-31
申请人： VIA Technologies, Inc.
发明人： Henry, G. Glenn , Parks, Terry
IPC分类号： G06F9/52
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.

3. 发明公开

EP3343372A1 DISTRIBUTED CACHE CLEANUP FOR ANALYTIC INSTANCE RUNS PROCESSING OPERATING DATA FROM INDUSTRIAL ASSETS 审中-公开
公开(公告)号：EP3343372A1
公开(公告)日：2018-07-04
申请号：EP17208813.0
申请日：2017-12-20
申请人： General Electric Company
发明人： CHANG, Tun , GUIN, Arnab
IPC分类号： G06F9/52 , G06F9/50 , G06F12/0806 , G06F12/084 , G06F12/0891
CPC分类号： G06Q10/06312 , G06F9/5072 , G06F9/52 , G06F12/0806 , G06F12/084 , G06F12/0891 , G06F2212/1032 , Y02P90/86
摘要： In some embodiments, a cloud-based services architecture 650 may receive operating data associated with a set of assets from a set of enterprise system devices 610. The cloud-based services architecture 650 may then process the received operating data. A plurality of computing platforms 630 may execute instance runs of a plurality of analytics 620, with each instance run being associated with an industrial asset. A distributed cache 660 may be shared by the plurality of analytic instance runs executing on the plurality of computing platforms 630. An orchestration run-time execution engine 640 may maintain an overall count value 665 that represents a number of analytic instance runs currently utilizing the distributed cache 660. Note that the distributed cache 660 may be emptied when the overall count value indicates that no analytic instance runs are still utilizing the distributed cache 660.

4. 发明授权

EP2979192B1 IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY 有权转让
公开(公告)号：EP2979192B1
公开(公告)日：2018-05-30
申请号：EP13879778.2
申请日：2013-03-28
申请人： Hewlett Packard Enterprise Development LP
发明人： LESARTRE, Gregg B. , BROOKS, Robert J. , GAITHER, Blaine D.
IPC分类号： G06F12/0804 , G06F12/0837
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/0837 , G06F2212/1032 , G06F2212/281
摘要： Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.

5. 发明公开

EP3270277A4 METHOD FOR DISPLAYING APPLICATION STORAGE SPACE AND TERMINAL 有权
公开(公告)号：EP3270277A4
公开(公告)日：2018-04-18
申请号：EP15888811
申请日：2015-04-16
申请人： HUAWEI TECH CO LTD
发明人： NI JING , WANG MENGJIAO
IPC分类号： G06F3/0481 , G06F3/0488
CPC分类号： G06F3/04817 , G06F3/04883 , G06F12/0891 , G06F2212/171 , G06F2212/60 , G06T11/001
摘要： Embodiments of the present invention disclose a method for displaying application storage space and a terminal, so as to enable a user to intuitively learn a use state of application storage space, so that the storage space can be cleaned in time to ensure normal and efficient running of a terminal. The method in the embodiments of the present invention includes: first displaying, by a terminal, a first icon on a desktop in first display mode; and when determining that storage space used by a first application corresponding to the first icon is greater than a preset storage threshold, displaying, by the terminal, the first icon in preset display mode that is different from the first display mode.

6. 发明公开

EP3285172A1 DATA CACHE REGION PREFETCHER 审中-公开
公开(公告)号：EP3285172A1
公开(公告)日：2018-02-21
申请号：EP16200806.4
申请日：2016-11-25
申请人： Advanced Micro Devices, Inc.
发明人： McCAULEY, Donald , JONES, William
IPC分类号： G06F12/0862 , G06F12/0886 , G06F12/0846
CPC分类号： G06F12/12 , G06F12/0848 , G06F12/0862 , G06F12/0886 , G06F12/0891 , G06F2212/1021 , G06F2212/6024 , G06F2212/6026
摘要： A data cache region prefetcher creates a region when a data cache miss occurs. Each region includes a predetermined range of data lines proximate to each data cache miss and is tagged with an associated instruction pointer register (RIP). The data cache region prefetcher compares subsequent memory requests against the predetermined range of data lines for each of the existing regions. For each match, the data cache region prefetcher sets an access bit and attempts to identify a pseudo-random access pattern based on the set access bits. The data cache region prefetcher increments or decrements appropriate counters to track how often the pseudo-random access pattern occurs. If the pseudo-random access pattern occurs frequently, then the next time a memory request is processed with the same RIP and pattern, the data cache region prefetcher prefetches the data lines in accordance with the pseudo-random access pattern for that RIP.
摘要翻译：数据缓存区域预取程序在发生数据缓存未命中时创建一个区域。每个区域包括靠近每个数据高速缓存未命中的预定范围的数据线，并且用相关联的指令指针寄存器（RIP）标记。数据高速缓存区预取器将后续存储器请求与每个现有区域的预定数据行范围进行比较。对于每个匹配，数据高速缓存区预取器设置一个访问位，并尝试基于设置的访问位来识别伪随机访问模式。数据高速缓存区域预取器递增或递减适当的计数器以跟踪伪随机访问模式发生的频率。如果伪随机访问模式频繁发生，则下一次以相同的RIP和模式处理存储器请求时，数据缓存区域预取器根据该RIP的伪随机访问模式来预取数据行。

7. 发明公开

EP3126987A4 USING ACCESS-FREQUENCY HIERARCHY FOR SELECTION OF EVICTION DESTINATION 审中-公开
公开(公告)号：EP3126987A4
公开(公告)日：2017-11-22
申请号：EP16754814
申请日：2016-01-27
申请人： STRATO SCALE LTD
发明人： RAPOPORT MIKE , GORDON ABEL , MAISLOS ARIEL
IPC分类号： G06F12/08 , G06F3/06 , G06F9/455
CPC分类号： G06F12/0891 , G06F3/0604 , G06F3/0605 , G06F3/061 , G06F3/0631 , G06F3/0649 , G06F3/0673 , G06F3/0685 , G06F2212/604
摘要： A method includes, in a computing system in which one or more workloads access memory pages in a memory, defining multiple memory-page lists, and specifying for each memory-page list a respective different scanning period. Access frequencies, with which the memory pages are accessed, are estimated continually by periodically checking the memory pages on each memory-page list in accordance with the scanning period specified for that memory-page list, and re-assigning the memory pages to the memory-page lists based on the estimated access frequencies. One or more of the memory pages are evicted from the memory based on a history of assignments of the memory pages to the memory-page lists.

8. 发明公开

EP3238077A1 FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH 有权
标题翻译：容错自动双列直插式内存模块刷新
公开(公告)号：EP3238077A1
公开(公告)日：2017-11-01
申请号：EP15874018.3
申请日：2015-11-24
申请人： Intel Corporation
发明人： JAYAKUMAR, Sarathy , KUMAR, Mohan J.
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F11/1441 , G06F1/30 , G06F1/3275 , G06F11/2015 , G06F12/0246 , G06F12/0638 , G06F12/0891 , G06F2212/205 , G06F2212/7208 , G06F2212/7209 , G11C5/04 , G11C5/148 , G11C7/20 , G11C14/0036 , G11C14/0045
摘要： Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed.
摘要翻译：描述了容错自动DIMM（双列直插式存储器模块）刷新或ADR的方法和装置。在一个实施例中，处理器包括非易失性存储器以存储来自处理器的一个或多个易失性缓冲器的数据。响应于导致系统重置或关闭的事件的发生，来自处理器的一个或多个易失性缓冲器的数据被存储到非易失性存储器中。其他实施例也被公开和要求保护。

9. 发明授权

EP1387259B1 Inter-processor control 有权
标题翻译：处理器间控制
公开(公告)号：EP1387259B1
公开(公告)日：2017-09-20
申请号：EP03291924.3
申请日：2003-07-30
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gérard , Lasserre, Serge
IPC分类号： G06F9/38
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/3802 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502 , Y02D10/13
摘要： A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the unsupported instruction. If there are less than a threshold number of consecutive supported instructions before the next unsupported instruction, the second processor loads the instructions in the first processor for execution so that the first processor does not fetch the instructions. If there are more than a threshold number of consecutive supported instructions before the next unsupported instruction, the first processor fetches and executes those instructions.
摘要翻译：一种系统包括耦合到第二处理器的第一处理器。第一和第二处理器连接到存储器。第一个处理器读取并执行支持的指令，直到检测到不支持的指令为止。第二个处理器执行不支持的指令。如果在下一个不支持的指令之前，连续支持指令的数量少于阈值数量，则第二处理器将指令加载到第一处理器中以供执行，以使第一处理器不获取指令。如果在下一个不支持的指令之前有超过阈值数量的连续支持指令，则第一个处理器将获取并执行这些指令。

10. 发明授权

EP1387253B1 Dynamic translation and execution of instructions within a processor 有权
标题翻译：在处理器内动态翻译和执行指令
公开(公告)号：EP1387253B1
公开(公告)日：2017-09-20
申请号：EP03291919.3
申请日：2003-07-30
申请人： Texas Instruments Incorporated , TEXAS INSTRUMENTS FRANCE
发明人： Chauvel, Gerard , D'Inverno, Dominique , Lasserre, Serge
IPC分类号： G06F12/08 , G06F9/318
CPC分类号： G06F9/30134 , G06F9/30101 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/321 , G06F9/325 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor may comprise fetch logic that retrieves instructions from memory, decode logic coupled to the fetch logic, and an active program counter selectable as either a first program counter or a second program counter. Further, an instruction may be replaced by a micro-sequence comprising one or more instructions and the active program counter also may switch between the first and second program counters.
摘要翻译：处理器可以包括从存储器检索指令的提取逻辑，与提取逻辑耦合的解码逻辑以及可选择为第一程序计数器或第二程序计数器的活动程序计数器。此外，指令可以被包括一个或多个指令的微序列替代，并且活动程序计数器也可以在第一和第二程序计数器之间切换。

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