专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2095222A1 PROCEDE ET CIRCUIT MULTIPLIEUR DE NOMBRES BINAIRES 审中-公开
标题翻译：方法和装置倍增的二进制数
公开(公告)号：EP2095222A1
公开(公告)日：2009-09-02
申请号：EP07731144.7
申请日：2007-03-15
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： The invention relates to a multiplier and a method using an adder network for multiplying two binary numbers X and Y defining a matrix [ E i n = x n-i y ], characterised in that it comprises: converting the initial matrix [ E i n = x n-i y ] into a matrix of the formula (I) using the formula (II); determining a first approximation U 0 n and R i-1 n-1 of the sum and the carry digit for the first two lines y0 and y1 of said matrix; using it as an input for the following approximation step that is repeated for all the following lines by successively adding the following lines yi+1 up to the last non-zero line according to a first series of predetermined propagation equations; ad propagating the carry digits R i-1 on the zero lines yi+1 according to a second series of predetermined propagation equations in order to obtain the final result of product P.

2. 发明公开

EP1403760A3 Method and system for high-speed multiplication 有权
标题翻译：快速繁殖的方法和装置
公开(公告)号：EP1403760A3
公开(公告)日：2006-08-02
申请号：EP03021760.8
申请日：2003-09-25
申请人： Broadcom Corporation
发明人： Wang, Minsheng
IPC分类号： G06F7/52
CPC分类号： G06F7/5332
摘要： A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows the actual multiplication process to proceed quickly. X is copied into a variable Z. Z is then manipulated to form the coded version of the multiplier. The bits of the multiplier X are read two at a time, starting with the least significant two bits. If the bit pair X i+1 X i is equal to 11, then 1 is added to Z i+2 . The process continues for successive non-overlapping pairs of bits, until the most significant three bits of X are reached. These last three bits are encoded using a table look-up process.

3. 发明授权

EP1543408B1 VORRICHTUNG UND VERFAHREN ZUM BERECHNEN EINER MULTIPLIKATION MIT EINER VERSCHIEBUNG DES MULTIPLIKANDEN 有权
标题翻译：装置和方法用于计算乘以被乘数的转变
公开(公告)号：EP1543408B1
公开(公告)日：2006-01-18
申请号：EP03782247.5
申请日：2003-11-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-Pierre INTEL Corporation , SEDLAK, Holger
IPC分类号： G06F7/72
CPC分类号： G06F7/722 , G06F7/5332
摘要： A device for calculating a modular multiplication comprises a unit for analyzing (100) positions of the multiplier by using a look-ahead algorithm in order to obtain a multiplication shifting value (sm). In addition, a unit for determining (104) an intermediate result shifting value is provided that determines a positive intermediate result shifting value. A unit (106) then calculates a multiplicand shifting value (sc) as a difference between the intermediate result shifting value (sz) and the multiplication shifting value (sm). The intermediate result from the previous iteration step and from the multiplicand are then shifted (108) by the corresponding shifting quantities (sc and sz) in order to then carry out a three-operand addition (112) with the shifted values optionally while taking look-ahead parameters (vn and vc) into consideration. The shifting of the intermediate result and of the multiplicand with regard to a fixed module enables the more efficient use of shifters since the multiplication shifting value (sm), which has a tendency to be large, does not dictate the shifter dimensioning.

4. 发明公开

EP2608015A1 System and method for implementing a multiplication 有权转让
标题翻译：系统和Verfahren zurAusführungeiner Multiplikation
公开(公告)号：EP2608015A1
公开(公告)日：2013-06-26
申请号：EP11194899.8
申请日：2011-12-21
申请人： IMEC , Katholieke Universiteit Leuven K.U. Leuven R&D , Samsung Electronics Co., Ltd.
发明人： Fasthuber, Robert , Raghavan, Praveen , Catthoor, Francky
IPC分类号： G06F9/30 , G06F7/533
CPC分类号： G06F7/523 , G06F7/5332 , G06F9/3001 , G06F9/30025
摘要： The present invention relates to a system for performing a multiplication, said system arranged for receiving a first data value (10) and comprising
- means (20) for calculating at run time a set of instructions for performing a multiplication using said first data value,
- storage means (50) for storing the set of instructions calculated at run time,
- multiplication means (40) arranged for receiving a second data value (30) and at least one instruction from the stored set of instructions and arranged for performing multiplication of the first and the second data value using said at least one instruction.
摘要翻译：本发明涉及一种用于执行乘法的系统，所述系统被安排用于接收第一数据值（10）并且包括 - 用于在运行时间计算用于使用所述第一数据值执行乘法的一组指令的装置（20） - 存储装置（50），用于存储在运行时间计算的指令集; - 乘法装置（40），被布置用于从所存储的指令集接收第二数据值（30）和至少一个指令，所述第一和第二数据值使用所述至少一个指令。

5. 发明授权

EP1323030B1 METHOD AND APPARATUS FOR INSTRUCTION SET ARCHITECTURE TO PERFORM PRIMARY AND SHADOW DIGITAL SIGNAL PROCESSING SUB-INSTRUCTIONS SIMULTANEOUSLY 有权
标题翻译：方法和设备的指令集架构为PRIMARY和阴影DIGITALSIGNALVERARBEITUNGSSUBBEFEHLEN同步实施
公开(公告)号：EP1323030B1
公开(公告)日：2010-03-17
申请号：EP01964189.3
申请日：2001-08-16
申请人： Intel Corporation
发明人： GANAPATHY, Kumar , KANAPATHIPILLAI, Ruban
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3877 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F9/3001 , G06F9/30025 , G06F9/30101 , G06F9/30138 , G06F9/30145 , G06F9/30149 , G06F9/30167 , G06F9/30192 , G06F9/381 , G06F9/382 , G06F9/383 , G06F9/3842 , G06F9/3853 , G06F9/3885 , G06F17/10
摘要： Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. A single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. Each signal processing unit of the ASSP includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. The present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction.

6. 发明授权

EP1866741B1 CANONICAL SIGNED DIGIT MULTIPLIER 有权
标题翻译：规范地DRAWN数字乘法器
公开(公告)号：EP1866741B1
公开(公告)日：2009-07-15
申请号：EP06727715.2
申请日：2006-03-23
申请人： NXP B.V.
发明人： PU, Tianyan , BI, Lei
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

7. 发明公开

EP1543408A1 VORRICHTUNG UND VERFAHREN ZUM BERECHNEN EINER MULTIPLIKATION MIT EINER VERSCHIEBUNG DES MULTIPLIKANDEN 有权
标题翻译：装置和方法用于计算乘以被乘数的转变
公开(公告)号：EP1543408A1
公开(公告)日：2005-06-22
申请号：EP03782247.5
申请日：2003-11-28
申请人： Infineon Technologies AG
发明人： FISCHER, Wieland , SEIFERT, Jean-PierreINTEL Corporation , SEDLAK, Holger
IPC分类号： G06F7/72
CPC分类号： G06F7/722 , G06F7/5332
摘要： A device for calculating a modular multiplication comprises a unit for analyzing (100) positions of the multiplier by using a look-ahead algorithm in order to obtain a multiplication shifting value (sm). In addition, a unit for determining (104) an intermediate result shifting value is provided that determines a positive intermediate result shifting value. A unit (106) then calculates a multiplicand shifting value (sc) as a difference between the intermediate result shifting value (sz) and the multiplication shifting value (sm). The intermediate result from the previous iteration step and from the multiplicand are then shifted (108) by the corresponding shifting quantities (sc and sz) in order to then carry out a three-operand addition (112) with the shifted values optionally while taking look-ahead parameters (vn and vc) into consideration. The shifting of the intermediate result and of the multiplicand with regard to a fixed module enables the more efficient use of shifters since the multiplication shifting value (sm), which has a tendency to be large, does not dictate the shifter dimensioning.

8. 发明公开

EP1228442A4 METHOD AND APPARATUS FOR SATURATED MULTIPLICATION AND ACCUMULATION IN AN APPLICATION SPECIFIC SIGNAL PROCESSOR 审中-公开
标题翻译：方法和设备饱和乘法器和积累应用程序中的特定信号处理器
公开(公告)号：EP1228442A4
公开(公告)日：2004-06-02
申请号：EP00989667
申请日：2000-10-19
申请人： INTEL CORP
发明人： GANAPATHY KUMAR , KANAPATHIPIILLAI RUBAN
IPC分类号： G06F7/52 , G06F7/53 , G06F7/533 , G06F7/544 , G06F9/302 , G06F9/38 , G06F17/10
CPC分类号： G06F17/10 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443
摘要： An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operation may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface (206), a buffer memory (210), a core processor (200A-D) for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where network is used to transceive packetized data and voice.

9. 发明公开

EP1323026A1 METHOD AND APPARATUS FOR FLEXIBLE DATA TYPES 有权
标题翻译：方法和装置灵活的数据类型
公开(公告)号：EP1323026A1
公开(公告)日：2003-07-02
申请号：EP01962212.5
申请日：2001-08-16
申请人： INTEL CORPORATION
发明人： GANAPATHY, Kumar , KANAPATHIPILLAI, Ruban
IPC分类号： G06F7/38 , G06F7/49 , G06F7/60 , G06F9/302 , G06F9/315
CPC分类号： G06F9/383 , G06F5/00 , G06F7/4806 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F7/57 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/381 , G06F9/3816 , G06F9/382 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F17/10
摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the present invention includes flexible data typing, permutation, and type matching operations (1101, 1102, 1104 and 1106). The flexible data typing, permutation and type matching of operands provides programming flexibility to support different filtering and DSP algorithms having different types of filter coefficients or data samples. A data typer and aligner within each signal processing unit within the ASSP supports flexible data typing, permutation, and type matching of operands of the instruction set architecture.

10. 发明公开

EP0773499A1 Multiplieur rapide pour multiplier un signal numérique par un signal périodique 失效
标题翻译： Schneller Multiplizierer zur Multiplikation eines digitalen Signal mit einem periodischen Signal
公开(公告)号：EP0773499A1
公开(公告)日：1997-05-14
申请号：EP96402348.5
申请日：1996-11-05
申请人： SEXTANT AVIONIQUE
发明人： Renard, Alain
IPC分类号： G06F7/52 , G06F1/03
CPC分类号： G06F7/5332 , G01S19/24 , G01S19/37 , G06F1/0328
摘要： L'invention concerne un circuit de multiplication numérique pour multiplier un signal numérique SN par une forme d'onde périodique, en principe sinusoïdale.
Ce circuit utilise un générateur numérique (10) de phase périodique Φ variant en dent de scie, et il utilise une approximation des échantillons d'une fonction KsinΦ par des sommes algébriques de puissances entières positives de deux pour chaque valeur de phase, K étant un coefficient identique pour toutes les valeurs de phase. Le produit de SN par ces sommes algébriques est rapide, simple à réaliser et ne nécessite pas une table de sinus. Un décodeur (12) recevant la phase Φ définit les puissances de deux à établir, et un circuit d'aiguillage (14) effectue les multiplications par des puissances de deux sous la commande du décodeur. Un ou deux additionneurs (ADD1, ADD2) établissent les sommes de puissances de deux. Le résultat est une valeur approchée du produit SN.K.sinΦ.
摘要翻译：该电路使用以锯齿形图案变化的周期相位（phi）的数字发生器（10）。对于每个相位值，它还使用函数的样本（K sin（phi））的近似值为正整数幂的代数和。 K是所有相位值相同的系数。数字信号（SN）和这些代数和的乘积是快速，简单的，只需要一个正弦表。接收相位（phi）的解码器（12）定义两个功能来建立。指示电路（14）在解码器的控制下通过两个功率来进行乘法运算。一个或两个加法器（ADD !, ADD2）建立两个加法器的总和。结果是接近产品SN.Ksin（phi）的值的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式