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1. 发明授权

EP2013705B1 ADDITIONNEUR N BITS ET PROCÉDÉ D'ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相关联的加入法
公开(公告)号：EP2013705B1
公开(公告)日：2015-11-11
申请号：EP07731319.5
申请日：2007-04-19
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/5063

2. 发明授权

EP1924904B1 ADDITIONNEUR N BITS ET PROCEDE D ' ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相应的添加方法
公开(公告)号：EP1924904B1
公开(公告)日：2009-07-22
申请号：EP06808073.8
申请日：2006-09-06
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/50
CPC分类号： G06F7/505
摘要： The invention concerns an n bit adder of first and second binary numbers, comprising first computing means with 2n inputs for receiving the n values of bits of said first and second binary numbers and an additional input for receiving an input carry digit (Z in ), said first computing means (MC1) being adapted to elaborate from each of the n pairs of bit values of the same significance, a carry digit propagating signal (t n ). The first computing means (MC1) is further adapted to elaborate n diagonal generation signals (q n ), the adder further comprising: estimating means (MEST) adapted to perform a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complementary of the value of the corresponding bit of significance of the first number; second computing means (MC2) connected to the first computing means (M1) and adapted to elaborate a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block (mcorr1, ..., mcorr14) comprising n outputs and adapted to apply to each estimated value of bit of significance k of said sum, k+1 corrections using said correcting signals, and to deliver in output the n bits of the sum of the first and second numbers.

3. 发明公开

EP2013705A1 ADDITIONNEUR N BITS ET PROCÉDÉ D'ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相关联的加入法
公开(公告)号：EP2013705A1
公开(公告)日：2009-01-14
申请号：EP07731319.5
申请日：2007-04-19
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/506 , G06F7/508
CPC分类号： G06F7/506 , G06F7/508 , G06F2207/5063
摘要： Adder for adding input signals comprising first (A) and second (B) binary input numbers, with N bits each. Said adder comprises determination means (MDET) capable of determining the bits of the sum of the input signals comprising estimating means including estimating blocks (BESTi) connected in series, each estimating block being capable of estimating each bit of said sum, and correction means (MCORi) capable of generating a correction signal so as to correct each estimated bit of said sum after each estimate, each correction signal of an estimated bit rank i of the sum being generated using the last rank i-1 estimated and corrected bit of the sum, the correction signal of said last rank i- 1 bit, and the last estimated and corrected rank i-2 bit of the sum.

4. 发明公开

EP2095222A1 PROCEDE ET CIRCUIT MULTIPLIEUR DE NOMBRES BINAIRES 审中-公开
标题翻译：方法和装置倍增的二进制数
公开(公告)号：EP2095222A1
公开(公告)日：2009-09-02
申请号：EP07731144.7
申请日：2007-03-15
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： The invention relates to a multiplier and a method using an adder network for multiplying two binary numbers X and Y defining a matrix [ E i n = x n-i y ], characterised in that it comprises: converting the initial matrix [ E i n = x n-i y ] into a matrix of the formula (I) using the formula (II); determining a first approximation U 0 n and R i-1 n-1 of the sum and the carry digit for the first two lines y0 and y1 of said matrix; using it as an input for the following approximation step that is repeated for all the following lines by successively adding the following lines yi+1 up to the last non-zero line according to a first series of predetermined propagation equations; ad propagating the carry digits R i-1 on the zero lines yi+1 according to a second series of predetermined propagation equations in order to obtain the final result of product P.

5. 发明公开

EP1924904A1 ADDITIONNEUR N BITS ET PROCEDE D ' ADDITION CORRESPONDANT 有权
标题翻译： N位加法器和相应的添加方法
公开(公告)号：EP1924904A1
公开(公告)日：2008-05-28
申请号：EP06808073.8
申请日：2006-09-06
申请人： S.A.R.L. Daniel Torno
发明人： TORNO, Daniel
IPC分类号： G06F7/50
CPC分类号： G06F7/505
摘要： The invention concerns an n bit adder of first and second binary numbers, comprising first computing means with 2n inputs for receiving the n values of bits of said first and second binary numbers and an additional input for receiving an input carry digit (Zin), said first computing means (MC1) being adapted to elaborate from each of the n pairs of bit values of the same significance, a carry digit propagating signal (tn). The first computing means (MC1) is further adapted to elaborate n diagonal generation signals (qn), the adder further comprising: estimating means (MEST) adapted to perform a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complementary of the value of the corresponding bit of significance of the first number; second computing means (MC2) connected to the first computing means (M1) and adapted to elaborate a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block (mcorr1, ..., mcorr14) comprising n outputs and adapted to apply to each estimated value of bit of significance k of said sum, k+1 corrections using said correcting signals, and to deliver in output the n bits of the sum of the first and second numbers.

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