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1. 发明公开

EP2067258A2 DEINTERLEAVER FOR A MULTI-STAGE INTERLEAVING SCHEME WITH PROCESSING OF BIT PAIRS 审中-公开
标题翻译：解交织器用于多阶段，交织位对加工
公开(公告)号：EP2067258A2
公开(公告)日：2009-06-10
申请号：EP07826331.6
申请日：2007-09-10
申请人： NXP B.V.
发明人： PU, Tianyan , SAWITZKI, Sergei V.
IPC分类号： H03M13/27
CPC分类号： H03M13/2796 , H03M13/271 , H03M13/276
摘要： A deinterleaver (10) for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means (12) for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory (16,18) for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator (20) for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

2. 发明公开

EP1872267A2 FAST FOURIER TRANSFORM ARCHITECTURE 审中-公开
标题翻译：体结构的快速傅立叶变换
公开(公告)号：EP1872267A2
公开(公告)日：2008-01-02
申请号：EP06727877.0
申请日：2006-04-11
申请人： NXP B.V.
发明人： PU, Tianyan , BI, Lei , TJIA, Jerome
IPC分类号： G06F17/14
CPC分类号： G06F17/142
摘要： A last fourier transform architecture has parallel data processing paths. Input data is applied to the parallel data processing paths in a repeating sequence, and processed in those paths. Data sequencers are used to combine the outputs from the data processing paths into the required sequence.

3. 发明公开

EP1866741A2 CANONICAL SIGNED DIGIT MULTIPLIER 有权
标题翻译：规范地DRAWN数字乘法器
公开(公告)号：EP1866741A2
公开(公告)日：2007-12-19
申请号：EP06727715.2
申请日：2006-03-23
申请人： NXP B.V.
发明人： PU, Tianyan , BI, Lei
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

4. 发明授权

EP2090051B1 METHOD AND APPARATUS FOR GENERATING DATA PACKETS FOR TRANSMISSION IN AN OFDM COMMUNICATION SYSTEM 有权
标题翻译：方法和装置用于生成数据包进行传输。在一个OFDM通信系统
公开(公告)号：EP2090051B1
公开(公告)日：2012-06-13
申请号：EP07826567.5
申请日：2007-09-27
申请人： NXP B.V.
发明人： PU, Tianyan
IPC分类号： H04L27/26
CPC分类号： H04L27/2626 , H04L27/2602 , H04W52/0212 , Y02D70/142 , Y02D70/144 , Y02D70/168
摘要： Method and apparatus for generating data packets for transmission in an orthogonal frequency division modulated communication system, in which preamble sequence for each packet is generated in the frequency domain or the time domain depending on at least two conditions to save power consumption and enable implementation in a single CMOS chip.
摘要翻译：用于在正交频分调制的通信系统中产生用于传输的数据分组的方法和设备中，在每个分组哪个前置码序列在频域中产生或时域取决于在至少两个条件，以节省功率消耗和一个能够实施单CMOS芯片。

5. 发明授权

EP1851614B1 LOW-POWER REGISTER ARRAY FOR FAST SHIFT OPERATIONS 有权
标题翻译：通风器装置具有低功耗，快速进行移位操作
公开(公告)号：EP1851614B1
公开(公告)日：2011-01-12
申请号：EP06727613.9
申请日：2006-02-08
申请人： NXP B.V.
发明人： BI, Lei , PU, Tianyan
IPC分类号： G06F5/10
CPC分类号： G06F5/10
摘要： A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data to enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient device that achieves high performance objectives while minimizing power consumption.

6. 发明公开

EP2090051A2 METHOD AND APPARATUS FOR GENERATING DATA PACKETS FOR TRANSMISSION IN AN OFDM COMMUNICATION SYSTEM 有权
标题翻译：方法和装置用于生成数据包进行传输。在一个OFDM通信系统
公开(公告)号：EP2090051A2
公开(公告)日：2009-08-19
申请号：EP07826567.5
申请日：2007-09-27
申请人： NXP B.V.
发明人： PU, Tianyan
IPC分类号： H04L27/26
CPC分类号： H04L27/2626 , H04L27/2602 , H04W52/0212 , Y02D70/142 , Y02D70/144 , Y02D70/168
摘要： Method and apparatus for generating data packets for transmission in an orthogonal frequency division modulated communication system, in which preamble sequence for each packet is generated in the frequency domain or the time domain depending on at least two conditions to save power consumption and enable implementation in a single CMOS chip.

7. 发明授权

EP1866741B1 CANONICAL SIGNED DIGIT MULTIPLIER 有权
标题翻译：规范地DRAWN数字乘法器
公开(公告)号：EP1866741B1
公开(公告)日：2009-07-15
申请号：EP06727715.2
申请日：2006-03-23
申请人： NXP B.V.
发明人： PU, Tianyan , BI, Lei
IPC分类号： G06F7/533
CPC分类号： G06F7/5332
摘要： A multiplier is able to multiply an input data value by a selected constant value in CSD form. The selected constant value has a plurality of pairs of bits, and the multiplier includes multiplexers, each controlled by a respective pair of bits of the selected constant value. Each of the multiplexers has a plurality of inputs, and is connected to receive the input data value, the inverse of the input data value, and all zeros on said inputs, and it is controlled such that it outputs either the input data value, the inverse of the input data value, or all zeros, depending on the values of the respective pair of bits of the selected constant value. Variable shift blocks are each connected to receive an input from a respective one of said multiplexers, and are each adapted to shift their received input by a first bit shift value or a second bit shift value, depending on the values of the respective pair of bits of the selected constant value, wherein the first bit shift value and the second bit shift value differ by 1. The multiplier also includes combination circuitry, for receiving the outputs from the plurality of shift blocks, and for combining the outputs from the plurality of shift blocks and applying further bit shifts, to form an output value equal to the result of multiplying the input data value by the selected constant value.

8. 发明公开

EP1851614A1 LOW-POWER REGISTER ARRAY FOR FAST SHIFT OPERATIONS 有权
标题翻译：通风器装置具有低功耗，快速进行移位操作
公开(公告)号：EP1851614A1
公开(公告)日：2007-11-07
申请号：EP06727613.9
申请日：2006-02-08
申请人： NXP B.V.
发明人： BI, Lei , PU, Tianyan
IPC分类号： G06F5/10
CPC分类号： G06F5/10
摘要： A data register (300) for use in a computer comprises a clock terminal (310) configured to receive a clock signal. A plurality of registers (320) are configured to selectively store data. A data input circuit (330) is coupled to the registers and configured to receive input data and selectively deliver the input data to the registers. A data output circuit (340) is coupled to the data registers and configured to selectively output the output data. A selector (350) is coupled to the data input circuit and the data output circuit, and configured to permit the input data to enter selected registers through the data input circuit and permit selected registers to output data through the data output circuit. The invention provides an efficient technique for loading the shift registers without a large number of simultaneous serial shifts. The result is a power-efficient device that achieves high performance objectives while minimizing power consumption.

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