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1. 发明授权

EP3905036B1 RECONFIGURABLE CIRCUIT, CORRESPONDING DEVICE, SYSTEM AND METHOD 有权
公开(公告)号：EP3905036B1
公开(公告)日：2024-08-28
申请号：EP21168368.5
申请日：2021-04-14
IPC分类号： G06F9/38
CPC分类号： G06F7/4806

2. 发明授权

EP0377604B1 A TRANSFORM PROCESSING CIRCUIT 失效
标题翻译： TRANSFORMATIONSVERARBEITUNGSSCHALTUNG
公开(公告)号：EP0377604B1
公开(公告)日：1995-12-20
申请号：EP88907212.0
申请日：1988-08-22
申请人： COMMONWEALTH SCIENTIFIC AND INDUSTRIAL RESEARCH ORGANISATION
发明人： HUA, Kien, Thanh , O'SULLIVAN, John, David , JACKA, Colin, Eric , BROWN, David, Ross
IPC分类号： G06F17/14 , G06F7/00 , G06F17/16 , G06F17/10 , G06F7/50 , G06F7/52 , G11C19/28 , G11C19/00
CPC分类号： G06F5/08 , G06F5/015 , G06F7/4806 , G06F17/142
摘要： The elements (36, 38, 40) of a transform processing circuit (30) are switchable to change the order of data in a data stream and/or to perform a fast Fourier transform (FFT) or inverse fast Fourier transform (IFFT) on the data stream. Each arithmetic circuit element (36) performs an M-point butterfly operation on complex sample points and includes an adder/subtractor (44) and a serial memory (46) capable of storing M/2 sample points. Each multiplication unit (38) performs an n-point complex twiddle factor operation on its input. The conjugator units (40) conjugate inputted sample points. All circuit elements (36, 38, 40) are connected to buses (42) by switches. These connections are switchable so that in one switch state data input at left terminal (32) flows to right terminal (34) and in another state data input at right terminal (34) flows to left terminal (32). The state of the bus switches also determines whether the circuit performs an FFT, an IFFT, or a bit reversal operation on input data. Transfer processing circuit (30) may be incorporated into an integrated circuit together with a complex multiplier and a multiplexer, the integrated circuit is capable of performing FFT and IFFT operations on vectors or on transformed vectors and is capable of performing vector multiplication.

3. 发明授权

EP3008618B1 COMPILER OPTIMIZATION FOR COMPLEX EXPONENTIAL CALCULATIONS 有权
标题翻译：复指数计算的编译器优化
公开(公告)号：EP3008618B1
公开(公告)日：2018-05-02
申请号：EP13886729.6
申请日：2013-06-14
申请人： Intel Corporation
发明人： BIKSHANDI, Ganesh , KIM, Daehyun
IPC分类号： G06F7/556 , G06F17/10
CPC分类号： G06F8/443 , G06F7/4806 , G06F7/556 , G06F8/4434 , G06F8/452 , G06F17/10 , G06F2207/5561
摘要： Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the parsed representation of the source code, and generates output code. During optimization, the compiler identifies a loop in the source code including a call to the exponential function having an argument that is a loop-invariant complex number multiplied by the loop index variable. The compiler tiles the loop to generate a pair of nested loops. The compiler generates code to pre-compute the exponential function and store the resulting values in a pair of coefficient arrays. The size of each coefficient array may be equal to the square root of the number of loop iterations. The compiler applies rewrite rules to replace the exponential function call with a multiplicative expression of one element from each of the coefficient arrays. Other embodiments are described and claimed.

4. 发明公开

EP3008618A4 COMPILER OPTIMIZATION FOR COMPLEX EXPONENTIAL CALCULATIONS 有权
标题翻译：编译器优化用于复指数演算
公开(公告)号：EP3008618A4
公开(公告)日：2017-01-11
申请号：EP13886729
申请日：2013-06-14
申请人： INTEL CORP
发明人： BIKSHANDI GANESH , KIM DAEHYUN
IPC分类号： G06F17/10 , G06F7/556 , G06F9/45
CPC分类号： G06F8/443 , G06F7/4806 , G06F7/556 , G06F8/4434 , G06F8/452 , G06F17/10 , G06F2207/5561
摘要： Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the parsed representation of the source code, and generates output code. During optimization, the compiler identifies a loop in the source code including a call to the exponential function having an argument that is a loop-invariant complex number multiplied by the loop index variable. The compiler tiles the loop to generate a pair of nested loops. The compiler generates code to pre-compute the exponential function and store the resulting values in a pair of coefficient arrays. The size of each coefficient array may be equal to the square root of the number of loop iterations. The compiler applies rewrite rules to replace the exponential function call with a multiplicative expression of one element from each of the coefficient arrays. Other embodiments are described and claimed.

5. 发明公开

EP1323026A1 METHOD AND APPARATUS FOR FLEXIBLE DATA TYPES 有权
标题翻译：方法和装置灵活的数据类型
公开(公告)号：EP1323026A1
公开(公告)日：2003-07-02
申请号：EP01962212.5
申请日：2001-08-16
申请人： INTEL CORPORATION
发明人： GANAPATHY, Kumar , KANAPATHIPILLAI, Ruban
IPC分类号： G06F7/38 , G06F7/49 , G06F7/60 , G06F9/302 , G06F9/315
CPC分类号： G06F9/383 , G06F5/00 , G06F7/4806 , G06F7/49921 , G06F7/5318 , G06F7/5332 , G06F7/5443 , G06F7/57 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30101 , G06F9/30145 , G06F9/30149 , G06F9/3016 , G06F9/30167 , G06F9/30181 , G06F9/30192 , G06F9/381 , G06F9/3816 , G06F9/382 , G06F9/3853 , G06F9/3877 , G06F9/3885 , G06F17/10
摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The ISA implemented with the ASSP, is adapted to DSP algorithmic structures. The ISA of the present invention includes flexible data typing, permutation, and type matching operations (1101, 1102, 1104 and 1106). The flexible data typing, permutation and type matching of operands provides programming flexibility to support different filtering and DSP algorithms having different types of filter coefficients or data samples. A data typer and aligner within each signal processing unit within the ASSP supports flexible data typing, permutation, and type matching of operands of the instruction set architecture.

6. 发明公开

EP1248993A2 A METHOD AND SYSTEM FOR PROCESSING COMPLEX NUMBERS 审中-公开
标题翻译：用于处理复数的方法和系统
公开(公告)号：EP1248993A2
公开(公告)日：2002-10-16
申请号：EP01901076.8
申请日：2001-01-05
申请人： Ipros Corporation
发明人： KHMELNIK, Solomon
IPC分类号： G06F17/10
CPC分类号： G06F7/4806 , G06F7/49
摘要： The invention provides a method and apparatus for storing complex number data in formats or codes which allow efficient complex number arithmetic operations to be performed and for performing such complex number arithmetic operations. According to one aspect of the invention, a method for coding complex numbers is provided for use in a data processing system. In response to receiving an instruction, two data elements representing the real and imaginary parts of a complex number are read. These two elements are then used to generate a single code for the complex number which is stored as a single data element. As a result of this coding, arithmetic operations on complex numbers may be performed on a single data element which contains both real and imaginary data. According to another aspect of the invention, a coprocessor is described. This coprocessor has stored therein data representing sequences of instructions which, when combined with certain unique circuitry also contained therein and executed, cause the coprocessor to perform the above described method and to perform complex number arithmetic operations.

7. 发明公开

EP0377604A4 A TRANSFORM PROCESSING CIRCUIT 失效
标题翻译：变压加工电路
公开(公告)号：EP0377604A4
公开(公告)日：1991-09-18
申请号：EP88907212
申请日：1988-08-22
申请人： THE COMMONWEALTH SCIENTIFIC AND INDUSTRIAL RESEARCH ORGANISATION
发明人： HUA, KIEN, THANH , O'SULLIVAN, JOHN, DAVID , JACKA, COLIN, ERIC , BROWN, DAVID, ROSS
IPC分类号： G06F5/01 , G06F5/08 , G06F7/48 , G06F17/14 , G06F15/332 , G06F7/00 , G06F7/50 , G06F7/52 , G06F15/31 , G06F15/347 , G11C19/00 , G11C19/28
CPC分类号： G06F5/08 , G06F5/015 , G06F7/4806 , G06F17/142

8. 发明公开

EP3035188A1 FIXED-POINT MULTIPLICATION BY ONE 有权
标题翻译： MITLIPLITIZIERUNG在FIXPUNKT MIT DEM WERT EINS
公开(公告)号：EP3035188A1
公开(公告)日：2016-06-22
申请号：EP15196356.8
申请日：2015-11-25
申请人： AptCore Ltd
发明人： WILDMAN, Leon , STYLES, Timothy
IPC分类号： G06F7/48 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/4806 , G06F2207/3808
摘要： A signal processing apparatus (10) comprises: a fixed-point compute unit (30) for operating on fractional 2's complement values without a mantissa; a memory unit (26) for storing a constant complex value to be used by the compute unit (30) to perform a complex arithmetic operation and a mapping unit (62), the mapping unit (62) being configured to map a complex value stored by the memory unit having a particular imaginary component, such as -1, to a value of unity, i.e. +1.
摘要翻译：信号处理装置（10）包括：用于在没有尾数的情况下对小数2的补码进行操作的定点计算单元（30）存储单元（26），用于存储要由计算单元（30）使用以执行复数运算的常数复数值和映射单元（62），所述映射单元（62）被配置为映射存储的复数值由具有特定虚部（例如-1）的存储单元提供为1的值，即+1。

9. 发明公开

EP1769334A1 COMPLEX LOGARITHMIC ALU 审中-公开
标题翻译：复杂的对数ALU
公开(公告)号：EP1769334A1
公开(公告)日：2007-04-04
申请号：EP05769168.5
申请日：2005-06-02
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)
发明人： DENT, Paul, Wilkinson
IPC分类号： G06F7/48
CPC分类号： G06F7/556 , G06F7/4806
摘要： The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up table used to determine logarithms of complex numbers, while a processor in the ALU generates an output logarithm based on complex input operands represented in logpolar format using the stored look-up table. In another exemplary embodiment, the ALU performs logarithmic arithmetic on real and complex numbers represented in logarithmic format. In this embodiment, the memory stores two look-up tables, one for determining logarithms of real numbers and one for determining logarithms of complex numbers, while the processor generates an output logarithm based on real or complex input operands represented in logarithmic format using the real or complex look-up tables, respectively.
摘要翻译：本发明描述了一种用于以对数格式表示的具有实数和/或复数的对数算术的方法和设备。在一个示例性实施例中，ALU对以对数格式表示的复数进行对数运算。根据该实施例，ALU中的存储器存储用于确定复数对数的查找表，而ALU中的处理器基于使用所存储的查找表以对数格式表示的复数输入操作数来生成输出对数。在另一个示例性实施例中，ALU对以对数格式表示的实数和复数进行对数运算。在该实施例中，存储器存储两个查询表，一个用于确定实数的对数，另一个用于确定复数的对数，而处理器基于使用实数的对数格式表示的实数或复数输入操作数生成输出对数或复杂的查找表。

10. 发明授权

EP0603794B1 Method and circuit for calculating the reciprocal of the amplitude of a vector 失效
标题翻译：方法和电路，用于计算一个矢量的振幅的倒数
公开(公告)号：EP0603794B1
公开(公告)日：1999-08-04
申请号：EP93120528.0
申请日：1993-12-20
申请人： FUJITSU LIMITED
发明人： Kaku, Takashi, Fujitsu Ltd., 1015 Kami-kodanaka , Miyazawa, Hideo, Fujitsu Ltd., 1015 Kami-kodanaka
IPC分类号： G06F7/552 , G06F17/16
CPC分类号： G06F7/5525 , G06F7/4806 , G06F7/552 , G06F17/10 , G06F2207/5521 , G06F2207/5525

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