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1. 发明公开

EP4413453A1 FLOATING-POINT LOGARITHMIC NUMBER SYSTEM SCALING SYSTEM FOR MACHINE LEARNING 审中-实审
公开(公告)号：EP4413453A1
公开(公告)日：2024-08-14
申请号：EP22879554.8
申请日：2022-10-11
申请人： Cassia.AI Inc.
发明人： TANDON, James
IPC分类号： G06F7/483 , G06F7/485 , G06F7/487 , G06F17/10 , G06F17/16
CPC分类号： Y02D10/00 , G06F7/4833

2. 发明公开

EP2596422A4 A CIRCULAR FLOATING-POINT NUMBER GENERATOR AND A CIRCULAR FLOATING-POINT NUMBER ADDER 审中-公开
标题翻译：循环滑动点发生器和圆弧滑动点加法器
公开(公告)号：EP2596422A4
公开(公告)日：2016-04-27
申请号：EP10854116
申请日：2010-07-01
申请人： ERICSSON TELEFON AB L M
发明人： ASANAKA KAZUNORI
IPC分类号： G06F7/483 , G06F7/499
CPC分类号： G06F7/4833 , G06F7/485 , G06F7/49915 , H03M7/24

3. 发明公开

EP0225488A3 Log encoding/decoding method 失效
标题翻译：日志编码器/解码器系统
公开(公告)号：EP0225488A3
公开(公告)日：1990-03-21
申请号：EP86115454.0
申请日：1986-11-07
申请人： International Business Machines Corporation
发明人： Mitchell, Joan LaVerne , Pennebaker, William Boone , Goertzel, Gerald
IPC分类号： G06F1/03 , G06F7/52 , H03M7/40
CPC分类号： G06F7/5235 , G06F1/0307 , G06F7/4833 , H03M7/4006
摘要： A high speed form of finite precision binary arithmetic coding comprises encoding/decoding performed in the logarithm domain, resulting in facilitated computation based on additions and subtractions rather than multiplications and divisions. In encoding and decoding, antilogs are used which are retrieved from an antilog table. The antilog table is characterized by the following constraints to assure decodability wherein for any two mantissas a and representing respective inputs to the antilog table:
(a) antilog (a + β) antilog (α)* antilog (β); at least when (α + β) is less than one; and (b) each antilog table output value is to be unique.

4. 发明公开

EP2443551A2 PROCESSING WITH COMPACT ARITHMETIC PROCESSING ELEMENT 审中-公开
标题翻译：用紧凑算术处理元素的处理
公开(公告)号：EP2443551A2
公开(公告)日：2012-04-25
申请号：EP10790095.3
申请日：2010-06-16
申请人： Singular Computing, LLC , Bates, Joseph
发明人： BATES, Joseph
IPC分类号： G06F9/38 , G06F9/46 , G06F13/14
CPC分类号： G06F7/483 , G06F7/38 , G06F7/4833 , G06F7/5235 , H03K19/17728
摘要： A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).
摘要翻译：诸如可编程和/或大规模并行处理器或其他设备的处理器或其他设备包括被设计用于执行算术运算的处理元件（可能但不一定包括例如加法，乘法，减法和除法中的一个或多个）对低精度但高动态范围（“LPHDR算术”）的数值进行处理。例如，这种处理器或其他设备可以在单个芯片上实现。无论是否在单个芯片上实现，在本发明的某些实施例中，处理器或其他设备中的LPHDR算术单元的数量显着超过（例如，至少超过三倍）算术单元的数量，如果有的话，在被设计来执行传统精度的高动态范围算术（例如32位或64位浮点算术）的处理器或其他设备中。

5. 发明公开

EP0054459A1 Dispositif de traitement de signaux logarithmiques, application à un radar fonctionnant en diversité de fréquence, et radar comportant un tel dispositif 有权
标题翻译：装置，用于处理对数信号使用频率分集雷达和雷达利用这样的装置。
公开(公告)号：EP0054459A1
公开(公告)日：1982-06-23
申请号：EP81401889.1
申请日：1981-11-27
申请人： THOMSON-CSF
发明人： Lassallette, Jean-Luc , Lepere, Guy , Rotat, Gérard
IPC分类号： G01S7/42 , G06F7/556
CPC分类号： G06F7/4833 , G01S7/42 , G06F1/0307
摘要： Dispositif de traitement de signaux logarithmiques destiné à délivrer le logarithme de la somme des signaux donnés sous le signe logarithme.
Dispositif fonctionnant en numérique et recevant au moins deux signaux logarithmiques, comportant un circuit soustracteur (19) effectuant la différence des signaux logarithmiques appliqués aux entrées, un circuit transcodeur (20) effectuant l'opération dans laquelle Log r1 et Log r2 sont respectivement les signaux appliqués aux entrées du dispositif et un circuit additionneur (21) réalisant l'opération et délivrant le signal recherché Log (r1 + r2).
Application aux radars à diversité de fréquence.

6. 发明公开

EP2443551A4 PROCESSING WITH COMPACT ARITHMETIC PROCESSING ELEMENT 审中-公开
标题翻译：具有结构紧凑算术处理单元处理
公开(公告)号：EP2443551A4
公开(公告)日：2012-12-12
申请号：EP10790095
申请日：2010-06-16
申请人： SINGULAR COMPUTING LLC , BATES JOSEPH
发明人： BATES JOSEPH
IPC分类号： G06F7/483 , G06F7/523 , H03K19/177
CPC分类号： G06F7/483 , G06F7/38 , G06F7/4833 , G06F7/5235 , H03K19/17728
摘要： A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

7. 发明授权

EP0366155B1 Logarithmic function arithmetic unit including means for separately processing pseudo division and multiplication 失效
标题翻译：对于对数函数运算单元，用于伪除法和乘法的单独的处理设有用于
公开(公告)号：EP0366155B1
公开(公告)日：1996-05-29
申请号：EP89120128.7
申请日：1989-10-30
申请人： NEC CORPORATION
发明人： Nakayama, Misayo c/o NEC Corporation
IPC分类号： G06F7/556 , G06F1/03
CPC分类号： G06F1/0307 , G06F7/4833 , G06F7/556

8. 发明授权

EP0225488B1 Log encoding/decoding method 失效
标题翻译：对数编码/解码方法。
公开(公告)号：EP0225488B1
公开(公告)日：1994-02-16
申请号：EP86115454.0
申请日：1986-11-07
申请人： International Business Machines Corporation
发明人： Mitchell, Joan LaVerne , Pennebaker, William Boone , Goertzel, Gerald
IPC分类号： G06F1/03 , G06F7/52 , H03M7/40
CPC分类号： G06F7/5235 , G06F1/0307 , G06F7/4833 , H03M7/4006

9. 发明公开

EP0366155A2 Logarithmic function arithmetic unit including means for separately processing pseudo division and multiplication 失效
标题翻译：对于对数函数运算单元，设置有用于伪除法和乘法的单独的处理。
公开(公告)号：EP0366155A2
公开(公告)日：1990-05-02
申请号：EP89120128.7
申请日：1989-10-30
申请人： NEC CORPORATION
发明人： Nakayama, Misayo c/o NEC Corporation
IPC分类号： G06F7/556 , G06F1/03
CPC分类号： G06F1/0307 , G06F7/4833 , G06F7/556
摘要： In a log e (1 + x/y) arithmetic unit by use of the STL algorithm, in order to reduce the arithmetic time, a pseudo division is at first effected by use of w = (2X k - Y k ) for k, initial values being mantissas X and Y of given x 2 -i ·X and y = 2 -j ·Y to produce X m and Y m , and thereafter, using X m and Y m as initial values a pseudo multiplication is effected by use of X k+1 = (X k + Γ k ) or X k+1 = X k /2 for k to obtain a mantissa of log e (1 + x/y). The unit comprises coefficient generator for producing k and Γ k , and first and second adder/subtractors accompanying with first and second registers for executing the pseudo division and the pseudo multipliction according to k and Γ k from the coefficient generator.
摘要翻译：在一个包厢（1 + X / Y）通过使用STL算法的运算单元中，为了减少运算时间，伪分割首先通过使用瓦特=的实现（2Xk - YK）对于k，初始值是尾数x和Y的给定的x 2的 .X和y = 2 .Y产生XM YM和，之后，用XM YM和作为初始值的伪乘法是通过使用X k的影响+ 1 =（值Xk + GAMMA K）或值Xk + 1 =值Xk / 2 k以获得包厢的尾数（1 + X / Y）。该单元包括系数发生器，用于生产K和K GAMMA，以及第一和第二加法器/减法器与第一和第二寄存器伴随用于从所述系数发生器执行伪分割和伪multiplictiongemäß到k和GAMMAķ。

10. 发明授权

EP0054459B1 Dispositif de traitement de signaux logarithmiques, application à un radar fonctionnant en diversité de fréquence, et radar comportant un tel dispositif 有权
标题翻译：对数信号处理器，应用于频率分集雷达和包含这种处理器的雷达
公开(公告)号：EP0054459B1
公开(公告)日：1985-09-04
申请号：EP81401889.1
申请日：1981-11-27
申请人： THOMSON-CSF
发明人： Lassallette, Jean-Luc , Lepere, Guy , Rotat, Gérard
IPC分类号： G01S7/42 , G06F7/556
CPC分类号： G06F7/4833 , G01S7/42 , G06F1/0307

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