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1. 发明授权

EP2431865B1 SEMICONDUCTOR INTEGRATED CIRCUIT AND INDEX CALCULATION METHOD 有权
公开(公告)号：EP2431865B1
公开(公告)日：2018-05-23
申请号：EP11760675.6
申请日：2011-04-12
申请人： NEC Corporation
发明人： SHIBAYAMA, Atsufumi
IPC分类号： G06F7/76 , G06F7/499
CPC分类号： H03M7/24 , G06F7/49915 , G06F7/49942
摘要： Provided is a semiconductor integrated circuit and an exponent calculation method that, when normalizing a plurality of data by a common exponent, speed up exponent calculation and reduce circuit scale and power consumption. When normalizing a plurality of data by a common exponent, a semiconductor integrated circuit 50 calculates the exponent of the plurality of data. Included is a bit string generator 51 that generates a second bit string containing bits having a transition value indicating that values of adjacent bits are different or a non-transition value indicating that values of adjacent bits are not different for each pair of adjacent bits of a first bit string constituting the data, and an exponent calculator 52 that calculates the exponent of the plurality of data based on a bit position of the transition value of a plurality of second bit strings generated from a plurality of first bit strings respectively constituting the plurality of data.

2. 发明公开

EP1782268A1 METHOD FOR AN EFFICIENT FLOATING POINT ALU 审中-公开
标题翻译：程序对于有效的浮动ALU
公开(公告)号：EP1782268A1
公开(公告)日：2007-05-09
申请号：EP05783849.2
申请日：2005-08-09
申请人： Analog Devices, Inc.
发明人： SRIVASTAVA, Saurbh
IPC分类号： G06F17/00 , G06F7/42 , G06F7/38
CPC分类号： G06F7/485 , G06F7/4991 , G06F7/49915
摘要： The present invention provides an improved technique for performing a near processing path (110) exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an apparatus (100) having a separate logic circuit for the near processing path (110) subtraction and the far processing path (140) subtraction generates exponent difference signals using only two least significant bits of exponents of the two floating point operands to perform the exponent difference.

3. 发明公开

EP0381191A2 Floating-point processor provided with high-speed detector of overflow and underflow exceptional conditions 失效
标题翻译：浮点处理器具有用于上溢和下溢异常高速检测器。
公开(公告)号：EP0381191A2
公开(公告)日：1990-08-08
申请号：EP90101910.9
申请日：1990-01-31
申请人： NEC CORPORATION
发明人： Kojima, Shingo
IPC分类号： G06F7/48
CPC分类号： G06F7/483 , G06F7/49915 , G06F7/49947 , G06F7/49957
摘要： A processor has an exception detector for detecting occurrence of Overflow und Underflow exceptions in floating-point data subjected to a rounding operation, said exception detector comprising first detection means for detecting whether the rounding operation to be executed is a rounding operation by raising or a rounding operation by truncating, means for unconditionally performing the rounding operation by raising on a mantissa part of said floating-point data to provide a modified mantissa part, second detection means for detecting a number of an exponent part of said floating-point data, and third detection means, responsive to detection outputs of said first and second detection means and overflow data of said modified mantissa part, for detecting whether or not Overflow or Underflow exception occurs in said floating-point data subjected to the rounding operation.
摘要翻译：处理器具有到异常检测器，用于在经受舍入手术浮点数据检测溢出和下溢异常的发生时，说的异常检测器包括第一检测装置，用于检测是否所述舍入手术将被执行的是通过提高或舍入的舍入运算通过截断的装置，用于通过提高在所述浮点数据的一个尾数部分，以提供经修改的尾数部分无条件执行舍入操作操作，第二检测装置，用于检测数目的所述浮点数据的指数部分，并且第三检测装置，响应于所述第一的检测输出和第二检测装置和所述的溢出数据修正的尾数部分，用于检测是否不上溢或下溢异常发生进行舍入运算。所述浮点数据。

4. 发明公开

EP0179796A4 FLOATING POINT ARITHMETIC SYSTEM AND METHOD WITH ANTICIPATION ROUNDING. 失效
标题翻译：滑动合成算术系统及初步设计方法。
公开(公告)号：EP0179796A4
公开(公告)日：1986-07-17
申请号：EP85901758
申请日：1985-03-14
申请人： ANALOGIC CORP
发明人： MATTEDI BRUNO ALLESSIO , WATARI HIROMICHI
IPC分类号： G06F7/485 , G06F7/38 , G06F7/50
CPC分类号： G06F7/485 , G06F7/49915 , G06F7/49936 , G06F7/49947

5. 发明公开

EP3301568A1 PROCESSING DENORMAL NUMBERS IN FMA HARDWARE 有权
标题翻译：处理FMA硬件中的正常数量
公开(公告)号：EP3301568A1
公开(公告)日：2018-04-04
申请号：EP17153226.0
申请日：2017-01-26
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： ELMER, Thomas
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3001 , G06F7/483 , G06F7/485 , G06F7/4876 , G06F7/49915 , G06F7/49936 , G06F7/49952 , G06F7/5443 , G06F9/30014 , G06F9/3861
摘要： A microprocessor includes FMA execution logic that determines whether to accumulate an accumulator operand C to the partial products of multiplier and multiplicand operands A and B in the partial product adder or in a second accumulation stage. The logic calculates an exponent delta of Aexp + Bexp - Cexp and determines the number of leading zeroes in C, if C is denormal. The microprocessor accumulates C with the partial products of A and B when the accumulation of C to the product of A and B could result in mass cancellation, when ExpDelta is greater than or equal to -K (where K is related to a width of a datapath in the partial product adder), and when a C isdenormal and its number of leading zeroes plus K exceeds-ExpDelta. The strategic use of resources in the partial product adder and second accumulation stage reduces latency.
摘要翻译：微处理器包括FMA执行逻辑，其确定是否将累加器操作数C累加到部分乘积加法器中或第二累加阶段中的乘数和被乘数操作数A和B的部分乘积。该逻辑计算Aexp + Bexp - Cexp的指数增量，并确定C中前导零的数量，如果C是非规范的。当ExpDelta大于或等于-K（其中K与a的宽度有关时，当C与A和B的乘积的积累可能导致质量消除时，微处理器用A和B的部分积积积C）在部分乘积加法器中的数据通路），以及当C isdenormal及其前导零的数量加上K超过-ExpDta时。部分产品加法器和第二个积累阶段中资源的战略使用减少了延迟。

6. 发明公开

EP1782268A4 METHOD FOR AN EFFICIENT FLOATING POINT ALU 审中-公开
标题翻译：程序对于有效的浮动ALU
公开(公告)号：EP1782268A4
公开(公告)日：2008-11-26
申请号：EP05783849
申请日：2005-08-09
申请人： ANALOG DEVICES INC
发明人： SRIVASTAVA SAURBH
IPC分类号： G06F17/00 , G06F7/38 , G06F7/42
CPC分类号： G06F7/485 , G06F7/4991 , G06F7/49915
摘要： The present invention provides an improved technique for performing a near processing path (110) exponent difference in an arithmetic logic unit (ALU) of a microprocessor. In one embodiment, an apparatus (100) having a separate logic circuit for the near processing path (110) subtraction and the far processing path (140) subtraction generates exponent difference signals using only two least significant bits of exponents of the two floating point operands to perform the exponent difference.

7. 发明授权

EP0164451B1 An arithmetic processing unit for executing a floating point operation 失效
标题翻译：用于执行浮点操作的算术处理单元
公开(公告)号：EP0164451B1
公开(公告)日：1992-05-20
申请号：EP84116332.2
申请日：1984-12-27
申请人： NEC CORPORATION
发明人： Tanaka, Hideo c/o NEC Corp.
IPC分类号： G06F5/00
CPC分类号： G06F7/485 , G06F7/49915

8. 发明公开

EP2596422A1 A CIRCULAR FLOATING-POINT NUMBER GENERATOR AND A CIRCULAR FLOATING-POINT NUMBER ADDER 审中-公开
标题翻译：一个循环浮点数生成器和一个循环浮点数加法器
公开(公告)号：EP2596422A1
公开(公告)日：2013-05-29
申请号：EP10854116.0
申请日：2010-07-01
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： ASANAKA, Kazunori
IPC分类号： G06F7/483
CPC分类号： G06F7/4833 , G06F7/485 , G06F7/49915 , H03M7/24
摘要： One aspect of the present invention will provide a circular floating-point number generator (400) for generating, from an input fixed-point number, a circular floating-point number including sign-bit field (S), exponent field (E), and circular-mantissa field (M). The generator assigns the input bits in the fixed-point number to a plurality of slots, generates the sign-bit field (S), generate the exponent field (E) based on a bit position of a leading significant bit, and generate the mantissa field (M) by extracting a first bit group and a second bit group and by providing a start bit of the first bit group after a last bit of the second bit group.
摘要翻译：本发明的一个方面将提供一种循环浮点数生成器（400），用于从输入的定点数生成包括符号位字段（S），指数字段（E），循环字段和圆形尾数字段（M）。生成器将定点数中的输入比特分配给多个时隙，生成符号比特字段（S），基于前导有效比特的比特位置生成指数字段（E），并生成尾数通过提取第一比特组和第二比特组，并且通过在第二比特组的最后比特之后提供第一比特组的开始比特来提供字段（M）。

9. 发明公开

EP2110740A1 COMPUTATION PROCESSOR, INFORMATION PROCESSOR, AND COMPUTING METHOD 有权
标题翻译： BERECHNUNGSVERFAHREN BERECHNUNGSPROZESSOR，INFORMATIONSPROZESSOR
公开(公告)号：EP2110740A1
公开(公告)日：2009-10-21
申请号：EP07714008.5
申请日：2007-02-09
申请人： Fujitsu Limited
发明人： TAJIRI, Kunihiko
IPC分类号： G06F7/499 , G06F7/483
CPC分类号： G06F7/49947 , G06F7/49915
摘要： To quickly determine a generation of a carry-out due to the rounding of floating point numbers, and speed up computation. To solve the problems, an LZ predictor (130) calculates a left shift amount from a computation result of the absolute value addition obtained by an absolute value adder (120), and outputs the amount to a left shifter (140) and a predicting unit (160). The left shifter (140) normalizes an absolute value addition result by left shifting the result by the left shift amount. The predicting unit (160) predicts whether blocks of four bits that form a region 1 and a region 2 are included in a rounding region after being normalized, and outputs a predicted result indicating whether each of bits included in the rounding region is 1. A CO detecting unit (170) detects a generation of a carry-out during the rounding by a rounding unit (150), by using the predicted result obtained by the predicting unit (160) and a part of bits of a normalized result obtained by the left shifter (140), and outputs one if the carry-out is generated.
摘要翻译：快速确定由于浮点数舍入导致的进位生成，并加快计算。为了解决这个问题，LZ预测器（130）根据由绝对值加法器（120）获得的绝对值相加的计算结果计算出左移量，并将该量输出到左移位器（140）和预测单元（160）。左移位器（140）通过将结果左移到左移位量来对绝对值相加结果进行归一化。预测单元（160）预测在归一化之后，形成区域1和区域2的四比特块是否被包括在舍入区域中，并且输出指示舍入区域中包括的每个比特是否为1的预测结果。 CO检测单元（170）通过使用由预测单元（160）获得的预测结果和通过预测单元（160）获得的归一化结果的位的一部分，来检测在舍入单元（150）舍入期间的进位输出左移位器（140），并且如果产生进位输出则输出一个。

10. 发明公开

EP2024816A1 MODE-BASED MULTIPLY-ADD PROCESSOR FOR DENORMAL OPERANDS 审中-公开
标题翻译：乘法加法器（乘加）用MODE FOR非规格化操作数
公开(公告)号：EP2024816A1
公开(公告)日：2009-02-18
申请号：EP07761472.5
申请日：2007-04-27
申请人： Qualcomm Incorporated
发明人： DOCKSER, Kenneth Alan , LALL, Pathik Sunil
IPC分类号： G06F7/499 , G06F7/487 , G06F7/544
CPC分类号： G06F7/49915 , G06F7/4876 , G06F7/5443 , G06F2207/3884
摘要： In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalize the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-f orwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream. If an unnormal intermediate result or a denormal final result will not occur, the addend may be restored to the multiply-add instruction and the add instruction converted to a NOP.

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