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1. 发明公开

EP2926344A4 ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE 有权
标题翻译： ROWHAMMER-ÜBERWACHUNGAUF DER BASIS GESPEICHERER ROWHAMMER-SCHWELLENWERTE
公开(公告)号：EP2926344A4
公开(公告)日：2016-11-23
申请号：EP13858832
申请日：2013-06-28
申请人： INTEL CORP
发明人： BAINS KULJIT , HALBERT JOHN B
IPC分类号： G11C11/4078 , G11C7/24 , G11C11/406
CPC分类号： G11C11/40611 , G06F13/1636 , G11C7/24 , G11C11/4078 , G11C11/408 , G11C29/50 , G11C29/50012
摘要： Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.
摘要翻译：存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内存在物理上相邻行的数据损坏风险的访问次数。检测逻辑从存储用于存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身上的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目。检测逻辑确定对存储器件的行的访问次数是否超过阈值。响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器设备执行针对物理上相邻的受害者行的刷新。

2. 发明公开

EP2926258A4 MEMORY MODULE INCLUDING MEMORY RESISTORS 有权转让
标题翻译： SPEICHERMODUL MITSPEICHERWIDERSTÄENEN
公开(公告)号：EP2926258A4
公开(公告)日：2016-06-01
申请号：EP12889100
申请日：2012-11-29
申请人： HEWLETT PACKARD DEVELOPMENT CO
发明人： BIGGS KENT E , SO CHI W , PROVENCHER MICHAEL A
IPC分类号： G06F13/14 , G06F9/06 , G06F9/44 , G06F9/455 , G06F12/02 , G06F13/16
CPC分类号： G06F12/0238 , G06F9/4401 , G06F9/45558 , G06F13/1636 , G06F2009/45583 , G06F2212/202 , G06F2212/251
摘要： A computing device includes, a memory component, a memory module including memory resistors, and a virtualization module. The virtualization module intercepts communication between an application and a memory component and directs the communication to the memory module including memory resistors. The virtualization module directs communication from the memory module to the application.
摘要翻译：计算设备包括存储器组件，包括存储器电阻的存储器模块和虚拟化模块。虚拟化模块拦截应用程序和存储器组件之间的通信，并将通信引导到包括存储器电阻器的存储器模块。虚拟化模块将通信从内存模块引导到应用程序。

3. 发明公开

EP2600253A4 SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 有权转让
标题翻译：半导体器件和数据处理系统
公开(公告)号：EP2600253A4
公开(公告)日：2014-01-01
申请号：EP11812196
申请日：2011-06-21
申请人： RENESAS ELECTRONICS CORP
发明人： SATO JUNKEI , HONDA NOBUHIKO
IPC分类号： G06F12/00 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/407
CPC分类号： G11C7/1072 , G06F13/1636 , G06F13/1689 , G06F13/4234 , G11C7/1057 , G11C7/1084 , G11C11/406 , G11C11/40603 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

4. 发明公开

EP1374247A2 METHOD AND APPARATUS FOR FORCING IDLE CYCLES TO ENABLE REFRESH OPERATIONS IN A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：和设备过载程序空闲周期来刷新操作的半导体存储器，以允许
公开(公告)号：EP1374247A2
公开(公告)日：2004-01-02
申请号：EP02717431.7
申请日：2002-02-12
申请人： Monolithic System Technology, Inc.
发明人： LEUNG, Wingyu
IPC分类号： G11C11/406
CPC分类号： G11C11/406 , G06F13/1636 , G11C11/40618 , G11C11/4076 , G11C2211/4061 , Y02D10/14
摘要： A method is provided for operating a memory system having a plurality of memory blocks. The method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks when the asserted timing signal is received; (3) within each of the memory blocks, performing a refresh operation if the refresh pending signal in the memory block is asserted and an idle cycle exists in the memory block; (4) within each of the memory blocks, asserting a refresh acknowledge signal if a refresh operation is performed in the memory block; (5) within each of the memory blocks, de-asserting the refresh pending signal in the memory block if the refresh acknowledge signal is asserted in the memory block; (6) asserting a refresh forcing signal if the refresh pending signal in any of the memory blocks is asserted when the timing signal is asserted; and (7) forcing an idle cycle in all of the memory blocks if the refresh forcing signal is asserted. A memory system for implementing this method is also provided.

5. 发明公开

EP0547758A3 Optional refresh 失效
标题翻译：可选刷新
公开(公告)号：EP0547758A3
公开(公告)日：1993-09-22
申请号：EP92310329.5
申请日：1992-11-12
申请人： SUN MICROSYSTEMS, INC.
发明人： Chesley, Gilman
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G06F13/1636 , G11C11/406
摘要： The present invention operates within a data processing system which utilizes dynamic memory requiring periodic refreshment. The data processing system includes a processor coupled to a memory controller which is in turn coupled to the dynamic memory. The memory controller includes a memory operation command queue for sequentially receiving memory operation commands from the processor and a refresh module for initiating refresh operations. The refresh module includes circuitry for initiating either a mandatory refresh operation or an optional refresh operation. Mandatory refresh operations are initiated at the conclusion of periodic intervals, unless an optional refresh operation has been initiated within the particular interval. An optional refresh operation is initiated within a particular interval if the memory operation command queue is empty. Optional refresh operations thereby serve to substitute for mandatory refresh operations, minimizing the system time lost to refresh operations.

6. 发明公开

EP0525749A1 Memory control device 失效
标题翻译： Speichersteueranordnung。
公开(公告)号：EP0525749A1
公开(公告)日：1993-02-03
申请号：EP92112950.8
申请日：1992-07-29
申请人： YOZAN INC. , SHARP KABUSHIKI KAISHA
发明人： Kumagai, Ryohei, c/o EZEL Inc. , Yang, Weikang, c/o EZEL Inc.
IPC分类号： G06F13/16
CPC分类号： G06F13/1636
摘要： The present invention has an object to provide a memory control device to be adapted to various demand using a standard DRAM.
This invention of a memory control device comprises a memory interface connected to a memory for outputting an address of the memory and controlling reading and writing, a plural number of input and output port connected to the memory interface through a local bus, a host interface connected to the memory interface through the local bus, a refresh control means for refreshing the memory through the memory interface, and an arbitration means for arbitrating requirements for refreshment from the refresh control means and for memory access from the input and output port and from host interface.
摘要翻译：本发明的目的是提供一种适应于使用标准DRAM的各种需求的存储器控制装置。本发明的存储器控制装置包括连接到存储器的存储器接口，用于输出存储器的地址并控制读取和写入，通过本地总线连接到存储器接口的多个输入和输出端口，连接的主机接口通过本地总线提供到存储器接口，用于通过存储器接口刷新存储器的刷新控制装置，以及仲裁装置，用于从刷新控制装置仲裁刷新的要求，以及从输入和输出端口以及从主机接口进行存储器访问。

7. 发明公开

EP0094042A2 Data processing apparatus wherein a system bus is shared by two or more circuits 失效
标题翻译：其中由两个或多个电路的系统共享的数据处理装置。
公开(公告)号：EP0094042A2
公开(公告)日：1983-11-16
申请号：EP83104433.4
申请日：1983-05-05
申请人： HITACHI, LTD.
发明人： Tachiuchi, Tsuguji , Honda, Toyota
IPC分类号： G06F3/04
CPC分类号： G11C11/406 , G06F13/1636 , G06F13/287 , G06F13/42
摘要： In accordance with the present invention, there is provided a data processing apparatus comprising an MPU (1) which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means (4) for latching said address signal, a memory (6) which must be refreshed, and changeover means (5) for connecting said memory to said MPU during a data signal period and connecting said memory to a refresh counter (2) during remaining periods.

8. 发明公开

EP4379561A1 MEMORY SYSTEM AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：EP4379561A1
公开(公告)日：2024-06-05
申请号：EP23205865.1
申请日：2023-10-25
申请人： Samsung Electronics Co., Ltd.
发明人： CHOI, Kyungeun , CHEONG, Wooseong
IPC分类号： G06F13/16 , G11C11/406
CPC分类号： G06F13/1636 , G11C11/40603 , G11C11/40618
摘要： Provided are a memory system and an operating method of the memory system. The memory system includes a memory controller configured to generate a first command and a second command in response to receiving a sequential command from a host, and a first memory device and a second memory device each configured to receive the first command and the second command, wherein the sequential command is a command to determine or indicate whether to access each of the first memory device and the second memory device, and the memory controller is further configured to determine whether to access at least one memory device among the first and second memory devices, transmit the first command to the first memory device when the first memory device is to be accessed, and transmit the second command to the second memory device when the second memory device is not to be accessed.

9. 发明公开

EP3357065A1 REFRESH TIMER SYNCHRONIZATION BETWEEN MEMORY CONTROLLER AND MEMORY 有权
公开(公告)号：EP3357065A1
公开(公告)日：2018-08-08
申请号：EP16759956.2
申请日：2016-08-25
申请人： Qualcomm Incorporated
发明人： JOSE, Edwin , DROP, Michael
IPC分类号： G11C11/406 , G06F13/16
CPC分类号： G11C11/40615 , G06F13/1636 , G11C11/40611 , G11C11/40626 , G11C11/4076 , G11C11/4087 , G11C2211/4067
摘要： A memory controller is configured to communicate to a DRAM an indication of when a most-recent memory-controller-triggered refresh cycle occurred prior to a transition to a self-refresh mode of operation in which the DRAM self-triggers its refresh cycles.

10. 发明公开

EP3259674A1 CIRCUIT DRAM MUNI D'UN PROCESSEUR INTEGRE 有权转让
标题翻译：具有集成处理器的DRAM电路
公开(公告)号：EP3259674A1
公开(公告)日：2017-12-27
申请号：EP16707914.4
申请日：2016-02-12
申请人： Upmem
发明人： DEVAUX, Fabrice , ROY, Jean-François
IPC分类号： G06F13/16
CPC分类号： G06F13/1673 , G06F13/1636
摘要： The invention relates to a memory circuit comprising: a memory network comprising at least one memory bank (418); a first processor (420); and a processor control interface for receiving instructions for processing data addressed to the first processor from a central processor (P1, P2), the processor control interface being designed to indicate to the central processor when the first processor has finished accessing at least one memory bank of the memory network, said memory banks becoming accessible for the central processor.

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