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1. 发明授权

EP2587384B1 Configurable data transfer in a digital signal processing system 有权
标题翻译：数字信号处理系统中的可配置数据传输
公开(公告)号：EP2587384B1
公开(公告)日：2017-07-12
申请号：EP12189414.1
申请日：2012-10-22
申请人： Imagination Technologies Limited
发明人： Anderson, Adrian John , Wass, Gary Christopher , Davies, Gareth John
IPC分类号： G06F13/28 , G06F9/54 , G06F15/167 , G06F9/38 , G06F12/10 , G06F9/30 , G06F9/50
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of hardware peripherals, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the hardware peripherals together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the hardware peripherals and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected hardware peripheral to read data from or write data to the memory device via its memory access channel.
摘要翻译：描述了用于在数字信号处理系统中传输数据的技术。在一个示例中，数字信号处理系统包括多个硬件外围设备，每个硬件外围设备连接到存储器访问控制器并且每个被配置为从存储器设备读取数据，对数据执行一个或多个操作，并且将数据写入到存储器设备。为避免将硬件外设硬连线在一起，并提供可配置的数字信号处理系统，多线程处理器控制硬件外设与存储器之间的数据传输。每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使选定的硬件外设能够从存储器读取数据或向存储器写入数据设备通过其存储器访问通道。

2. 发明授权

EP2895959B1 PROCÉDÉ D'ACCÈS À L'ENSEMBLE DES CELLULES D'UNE ZONE MÉMOIRE À DES FINS D'ÉCRITURE OU DE LECTURE DE BLOCS DE DONNÉES DANS LESDITES CELLULES 有权转让
标题翻译：方法用于进入细胞的存储区域中安排用于写入或读取数据块在这些细胞
公开(公告)号：EP2895959B1
公开(公告)日：2016-12-14
申请号：EP13814974.5
申请日：2013-12-23
申请人： Morpho
发明人： SERE, Ahmadou , BOULET, Frédéric
IPC分类号： G06F12/02 , G06F12/14
CPC分类号： G06F12/0284 , G06F7/582 , G06F12/0292 , G06F12/1408 , G06F2212/251

3. 发明公开

EP2842041A4 DATA PROCESSING SYSTEM AND METHOD FOR OPERATING A DATA PROCESSING SYSTEM 有权转让
标题翻译：数据处理系统和操作数据处理系统的方法
公开(公告)号：EP2842041A4
公开(公告)日：2015-12-09
申请号：EP12875463
申请日：2012-04-23
申请人： FREESCALE SEMICONDUCTOR INC
发明人： COSTIN DANIEL IONEL
IPC分类号： G06F21/54 , G06F9/06 , G06F9/42 , G06F12/16
CPC分类号： G06F12/023 , G06F9/06 , G06F9/30043 , G06F12/16 , G06F21/52 , G06F21/54 , G06F21/71 , G06F2212/251
摘要： A data processing system comprising a processing unit, a first memory, and a second memory, wherein the data processing system is arranged to hardware protect the second memory when a write access to the first memory is executed, wherein the processing unit is arranged to execute a program having at least one jump instruction and at least one return instruction, wherein the processing unit is arranged to store a program stack in the first memory, wherein the processing unit is arranged to store a return address on the program stack and to store a return address copy in the second memory when the at least one jump instruction is executed, and wherein the processing unit is arranged to compare the return address with the return address copy when the at least one return instruction is executed.

4. 发明公开

EP2891069A1 HIGH PERFORMANCE PERSISTENT MEMORY 审中-公开
标题翻译：永久内存高性能
公开(公告)号：EP2891069A1
公开(公告)日：2015-07-08
申请号：EP12883648.3
申请日：2012-08-28
申请人： Hewlett-Packard Development Company, L.P.
发明人： LI, Sheng , YOON, Doe Hyun , JOUPPI, Norman Paul
IPC分类号： G06F13/14 , G11C16/06
CPC分类号： G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F11/1471 , G06F12/0891 , G06F2003/0691 , G06F2212/1032 , G06F2212/202 , G06F2212/222 , G06F2212/251 , G06F2212/304 , G11C16/06
摘要： A method of performing data transactions in a high performance persistent memory comprising, with a processor, updating data by writing new data to non-volatile memory (NVM) and receiving a done signal from a transaction accelerator communicatively coupled to the NVM. An apparatus for high performance persistent memory, comprising a processor, a memory controller communicatively coupled to the processor, and non-volatile memory communicatively coupled to the memory controller and processor, the non-volatile memory comprising an ACID transaction accelerator, in which the processor updates data on the non-volatile memory (NVM) by writing new data to the NVM, and receives a done signal from the an ACID transaction accelerator when the data has been updated.

5. 发明公开

EP2587384A1 Configurable data transfer in a digital signal processing system 有权
标题翻译： Konfigurierbarer数码转换器在einem digitalen Signalverarbeitungssystem
公开(公告)号：EP2587384A1
公开(公告)日：2013-05-01
申请号：EP12189414.1
申请日：2012-10-22
申请人： Imagination Technologies Limited
发明人： Anderson, Adrian John , Wass, Gary Christopher , Davies, Gareth John
IPC分类号： G06F13/28 , G06F9/54 , G06F15/167 , G06F9/38
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of hardware peripherals, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the hardware peripherals together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the hardware peripherals and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected hardware peripheral to read data from or write data to the memory device via its memory access channel.
摘要翻译：描述了一种用于在数字信号处理系统中传送数据的技术。在一个示例中，数字信号处理系统包括多个硬件外围设备，每个硬件外围设备连接到存储器访问控制器，并且每个硬件外围设备被配置为从存储器设备读取数据，对数据执行一个或多个操作，并将数据写入存储器设备。为了避免将硬件外围设备硬连线在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制硬件外围设备和存储器之间的数据传输。每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使所选择的硬件外围设备从存储器读取数据或向存储器写入数据设备通过其存储器访问通道。

6. 发明公开

EP2541404A1 Technique for task sequence execution 失效
标题翻译： Technik zurArbeitssequenzausführung
公开(公告)号：EP2541404A1
公开(公告)日：2013-01-02
申请号：EP11005362.6
申请日：2011-06-30
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： Varshney, Deepak
IPC分类号： G06F9/48 , G06F12/08
CPC分类号： G06F9/48 , G06F9/4881 , G06F12/08 , G06F2212/251 , G06F2212/253 , Y02D10/13 , Y02D10/24
摘要： A technique for executing a task sequence on a computing system comprising a multiple task processor having an on-chip memory and further comprising an external memory connected to the multiple task processor is provided. A method implementation of the technique comprises transferring load module data from the external memory into the on-chip memory in order to generate a load module sequence within the on-chip memory, wherein the generation of a load module of the load module sequence comprises the following processes: determining which parts of the load module are currently stored within the on-chip memory, and transferring only load module data from the external memory into the on-chip memory for parts of the load module which are currently not stored within the on-chip memory, wherein each load module of the load module sequence is generated within an individual address range of the on-chip memory which is chosen in dependence on the load module sequence. The method implementation further comprises executing the task sequence by running the load module sequence.
摘要翻译：一种用于在计算系统上执行任务序列的技术，包括具有片上存储器的多任务处理器，并且还包括连接到所述多任务处理器的外部存储器。该技术的方法实现包括将负载模块数据从外部存储器转移到片上存储器中，以便在片内存储器内生成加载模块序列，其中负载模块序列的负载模块的生成包括以下过程：确定当前存储在片上存储器中的负载模块的哪些部分，并且仅将负载模块数据从外部存储器传送到片上存储器中用于负载模块的当前未存储在其中的部分芯片存储器，其中负载模块序列的每个负载模块在片上存储器的单独的地址范围内产生，其根据负载模块序列被选择。方法实现还包括通过运行加载模块序列来执行任务序列。

7. 发明公开

EP2344951A4 CONDITIONAL PROCESSING METHOD AND APPARATUS 有权
标题翻译：设备和方法处理有条件
公开(公告)号：EP2344951A4
公开(公告)日：2012-05-16
申请号：EP09823866
申请日：2009-10-30
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HWANG SEO YOUNG , SONG JAE YEON , LEE KOOK HEUI
IPC分类号： G06F9/45
CPC分类号： G06F12/023 , G06F8/427 , G06F9/44505 , G06F17/2247 , G06F17/2705 , G06F2212/251
摘要： A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method includes generating a parse tree by loading a plurality of nodes of data structured based on a declarative description language in a memory in series; evaluating, when a parsing switch node having an attribute describing a condition for conditional processing exists among the nodes, child nodes of the parsing switch node according to the attribute; loading only the child nodes fulfilling the attribute in the memory; and outputting the child nodes retained on the memory.

8. 发明公开

EP2344951A2 CONDITIONAL PROCESSING METHOD AND APPARATUS 有权
标题翻译：设备和方法处理有条件
公开(公告)号：EP2344951A2
公开(公告)日：2011-07-20
申请号：EP09823866.0
申请日：2009-10-30
申请人： Samsung Electronics Co., Ltd.
发明人： HWANG, Seo Young , SONG, Jae Yeon , LEE, Kook Heui
IPC分类号： G06F9/45
CPC分类号： G06F12/023 , G06F8/427 , G06F9/44505 , G06F17/2247 , G06F17/2705 , G06F2212/251
摘要： A conditional processing method and apparatus for efficient memory management are provided. A conditional processing method of the present inventions includes generating a parse tree by loading a plurality of nodes of data structured based on a declarative description language in a memory in series; evaluating, when a parsing switch node having an attribute describing a condition for conditional processing exists among the nodes, child nodes of the parsing switch node according to the attribute; loading only the child nodes fulfilling the attribute in the memory; and outputting the child nodes retained on the memory.

9. 发明公开

EP2005305A1 MEMORY COMPRESSION IN INFORMATION HANDLING SYSTEMS 审中-公开
标题翻译：内存压缩在信息处理系统
公开(公告)号：EP2005305A1
公开(公告)日：2008-12-24
申请号：EP07726716.9
申请日：2007-03-08
申请人： International Business Machines Corporation
发明人： GSCHWIND, Michael, Karl , MINOR, Barry
IPC分类号： G06F12/04
CPC分类号： G06F12/04 , G06F9/30178 , G06F12/08 , G06F2212/251 , G06F2212/253 , G06F2212/401
摘要： The disclosed heterogeneous processor compresses information to more efficiently store the information in a system memory coupled to the processor. The heterogeneous processor includes a general purpose processor core coupled to one or more processor cores that exhibit an architecture different from the architecture of the general purpose processor core. In one embodiment, the processor dedicates a processor core other than the general purpose processor core to memory compression and decompression tasks. In another embodiment, system memory stores both compressed information and uncompressed information.

10. 发明公开

EP0930574A2 Parallel processor and processing method 审中-公开
标题翻译： Paralleler Prozessor und Verarbeitungsverfahren
公开(公告)号：EP0930574A2
公开(公告)日：1999-07-21
申请号：EP99400094.1
申请日：1999-01-15
申请人： SONY CORPORATION
发明人： Imamura, Yoshihiko
IPC分类号： G06F15/76 , G06F12/14
CPC分类号： G06F12/08 , G06F12/0811 , G06F2212/251 , G06F2212/253
摘要： A parallel processor (21) capable of exhibiting a high processing performance, which when receiving as input access requests generating page faults to sub-banks (27 1 , 27 2 , 27 3 ) from a plurality of processor elements (23 1 , 23 2 , ...23 n ) connected to a common bus (22) and another access request is input while data is being transferred between sub-banks (27 1 , 27 2 , 27 3 ) and an external memory (7) via an external access bus (26) in response to the input access requests, a shared memory (24) stores the other access request in a request queue and makes a control circuit execute the stored access request when the stored access request does not generate a page fault.
摘要翻译：一种能够表现出高处理性能的并行处理器（21），当从多个处理器元件（231,232，... 23n）接收作为输入访问请求的子行（271,272,273）时，），并且响应于所述公共总线（22），在经由外部存取总线（26）在子存储体（271,272,273）和外部存储器（7）之间传送数据的同时输入另一访问请求输入访问请求，共享存储器（24）将其他访问请求存储在请求队列中，并且当所存储的访问请求不产生页面错误时，控制电路执行存储的访问请求。

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