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1. 发明公开

EP3382556A1 MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS 审中-公开
公开(公告)号：EP3382556A1
公开(公告)日：2018-10-03
申请号：EP18165216.5
申请日：2011-09-30
申请人： INTEL Corporation
发明人： Nale, Bill , RAMANUJAN, Raj K. , SWAMINATHAN, Muthukumar P. , THOMAS, Tessil , POLEPEDDI, Taarinya
IPC分类号： G06F12/08 , G06F12/00 , G06F11/10 , G06F13/14 , G06F13/16 , G06F9/46 , G06F13/42 , G06F13/36 , G06F12/02 , G06F12/0868 , G06F12/0811 , G06F13/40
CPC分类号： G06F13/1694 , G06F9/467 , G06F11/1064 , G06F12/0238 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0868 , G06F12/0897 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F13/4234 , G06F2212/1008 , G06F2212/1016 , G06F2212/1044 , G06F2212/2024 , G06F2212/7203 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

2. 发明授权

EP2995051B1 SYNCHRONOUS DATA-LINK THROUGHPUT ENHANCEMENT TECHNIQUE BASED ON DATA SIGNAL DUTY-CYCLE AND PHASE MODULATION/DEMODULATION 有权
公开(公告)号：EP2995051B1
公开(公告)日：2018-09-12
申请号：EP14727128.2
申请日：2014-04-23
申请人： Qualcomm Incorporated
发明人： MISHRA, Lalan J. , CHUN, Dexter T. , DATTA, Animesh
IPC分类号： H04L25/49
CPC分类号： G06F13/42 , G06F13/1689 , G06F13/4234 , G06F13/4243 , G06F13/4282 , G11C7/10 , G11C7/222 , H04L7/0008 , H04L7/0037 , H04L25/4902
摘要： A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

3. 发明公开

EP2992436A4 MEMORY NETWORK TO ROUTE MEMORY TRAFFIC AND I/O TRAFFIC 无效转让
公开(公告)号：EP2992436A4
公开(公告)日：2018-04-04
申请号：EP13883783
申请日：2013-04-30
申请人： HEWLETT PACKARD ENTPR DEVELOPMENT LP
发明人： BARRON DWIGHT L , FARABOSCHI PAOLO , JOUPPI NORMAN PAUL , KRAUSE MICHAEL R , LI SHENG
IPC分类号： G06F13/14 , G06F13/38
CPC分类号： G06F12/0813 , G06F12/0815 , G06F12/0824 , G06F12/0835 , G06F13/28 , G06F13/4022 , G06F13/4234 , G06F15/167 , G06F2212/1016 , G06F2212/1048 , G06F2212/621
摘要： According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

4. 发明公开

EP3299962A1 COMPUTER, AND METHOD AND APPARATUS FOR CONTROLLING QUALITY OF SERVICE 有权
标题翻译：计算机，以及用于控制服务质量的方法和设备
公开(公告)号：EP3299962A1
公开(公告)日：2018-03-28
申请号：EP16850234.2
申请日：2016-08-31
申请人： Huawei Technologies Co., Ltd.
发明人： ZHANG, Jian
IPC分类号： G06F9/50
CPC分类号： G06F9/5016 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F12/1009 , G06F13/1621 , G06F13/1657 , G06F13/4234 , G06F2212/657
摘要： The present invention discloses a computer and a quality of service control method and apparatus, and pertains to the computer field. The method includes: allocating, to at least one container of a computer, a container ID that corresponds one-to-one to the container; sending a bus request to a system bus, where the bus request carries the container ID and a hardware device ID of a hardware device used by the container indicated by the container ID; searching, according to the bus request, for a quality of service QoS parameter corresponding to both the container ID and the hardware device ID, where the QoS parameter is stored in a bus management module; and configuring, according to the found QoS parameter, a resource required when the container corresponding to the QoS parameter uses the hardware device corresponding to the QoS parameter. According to the present invention, the system bus may perform corresponding QoS control according to the QoS parameter corresponding to both the container ID and the hardware device ID, so that the hardware device allocated to the container can meet resource requirements of a process group in the container.
摘要翻译：本发明公开了一种计算机和服务质量控制方法及装置，属于计算机领域。该方法包括：向计算机的至少一个容器分配与容器一一对应的容器ID; 向系统总线发送总线请求，所述总线请求中携带容器ID指示的容器使用的硬件设备的容器ID和硬件设备ID; 根据所述总线请求查找与所述容器标识和所述硬件设备标识对应的服务质量QoS参数，所述QoS参数存储在总线管理模块中; 根据查找到的所述QoS参数，配置所述QoS参数对应的容器使用所述QoS参数对应的硬件设备时所需的资源。根据本发明，系统总线可以根据容器ID和硬件设备ID两者对应的QoS参数进行相应的QoS控制，以使分配给该容器的硬件设备可以满足该容器中的进程组的资源需求容器。

5. 发明公开

EP3279788A1 ACCESS METHOD, DEVICE AND SYSTEM FOR EXPANDING MEMORY 有权
标题翻译：用于扩展存储器的访问方法，设备和系统
公开(公告)号：EP3279788A1
公开(公告)日：2018-02-07
申请号：EP16782466.3
申请日：2016-02-03
申请人： Huawei Technologies Co. Ltd.
发明人： CUI, Zehan , CHEN, Mingyu , LIU, Yao , RUAN, Yuan
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/06 , G06F3/0619 , G06F3/065 , G06F3/0656 , G06F12/0215 , G06F12/0623 , G06F13/1673 , G06F13/1689 , G06F13/1694 , G06F13/4234 , G06F2212/1008 , G06F2212/1024 , G06F2213/0064
摘要： A method for accessing an extended memory, a device, and a system are disclosed. The method includes: receiving N+1 memory access requests serially sent by a processor system in a computer, where access addresses in all the memory access requests are different from each other and point to a same physical address, the physical address is a storage address of to-be-accessed data in the extended memory, N≥1, and N is an integer; when a first memory access request is received, sending a read request to the extended memory, and returning a specific response message to a processor; in a process of reading the to-be-accessed data from the extended memory, each time a memory access request is received, returning a specific response message to the processor within a delay specified in a memory bus protocol until the to-be-accessed data is written into a data buffer; and then returning the to-be-accessed data to the processor system.
摘要翻译：公开了一种用于访问扩展存储器，设备和系统的方法。该方法包括：接收计算机中处理器系统串行发送的N + 1个内存访问请求，其中所有内存访问请求中的访问地址彼此不同且指向相同的物理地址，所述物理地址为存储地址扩展存储器中待访问数据的N≥1，N为整数; 当接收到第一存储器访问请求时，向所述扩展存储器发送读取请求，并且向处理器返回特定响应消息; 在从扩展存储器读取待访问数据的过程中，每当接收到存储器访问请求时，在存储器总线协议规定的延迟内向处理器返回特定的响应消息，直到要被访问数据被写入数据缓冲区; 然后将待访问数据返回给处理器系统。

6. 发明公开

EP3255552A1 MEMORY AND METHOD FOR OPERATING A MEMORY WITH INTERRUPTIBLE COMMAND SEQUENCE 有权
标题翻译：用于操作具有可中断命令序列的存储器的存储器和方法
公开(公告)号：EP3255552A1
公开(公告)日：2017-12-13
申请号：EP17167031.8
申请日：2017-04-19
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Chen, Ken-Hui , Chang, Kuen-Long , Lo, Su-Chueh , Liao, Chun-Yu
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/4234 , G06F13/1631 , G06F13/1673 , G06F13/4291
摘要： A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.
摘要翻译：存储器设备包括允许命令协议的命令逻辑，该命令协议允许第一命令序列（诸如页面写入序列）的中断，然后直接继续接收并解码诸如读取序列的第二命令序列而没有等待时间关联，完成第一个命令序列。而且，命令逻辑被配置为在第二命令序列及其相关联的嵌入操作已经完成之后响应于第三命令序列，其完成了中断的第一命令序列并且使得能够执行由第一命令序列标识的嵌入操作。描述了支持这种协议的存储器控制器。

7. 发明公开

EP3188032A1 STOCKAGE DE DONNÉES DANS UNE MÉMOIRE FLASH 有权转让
标题翻译：将数据存储在闪存中
公开(公告)号：EP3188032A1
公开(公告)日：2017-07-05
申请号：EP16161615.6
申请日：2016-03-22
申请人： PROTON WORLD INTERNATIONAL N.V.
发明人： AHSSINI, Youssef , RESTIAU, Guy
IPC分类号： G06F13/42
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/064 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0246 , G06F12/08 , G06F13/42 , G06F13/4234 , G06F2212/152 , G06F2212/214 , G06F2212/657 , G06F2212/7202 , H04W4/80
摘要： L'invention concerne un procédé de stockage de données dans une mémoire non volatile, lors d'une transaction hors ligne entre un circuit contenant ladite mémoire et un terminal, dans lequel : une page de la mémoire est affectée à chaque transaction ; les données de chaque transaction sont stockées de façon séquentielle dans la page correspondante ; et la page affectée à une transaction est verrouillée en écriture à la fin de la transaction correspondante.
摘要翻译：本发明涉及在非易失性存储器的数据存储方法，在一个事务离线含有所述存储器和一个终端的电路，其中，所述存储器的一页被指定给每个事务之间; 每个交易的数据被顺序存储在相应的页面中; 并且分配给事务的页面在相应事务结束时被写入锁定。

8. 发明公开

EP3025239A4 NON-VOLATILE MEMORY INTERFACE 有权
标题翻译：不挥发存储器接口
公开(公告)号：EP3025239A4
公开(公告)日：2017-04-05
申请号：EP13890241
申请日：2013-07-26
申请人： INTEL CORP
发明人： OOI ENG HUN , ROYER ROBERT J JR , WILLIAMS MICHAEL W , WILCOX JEFFREY R , TRIVEDI RITESH B , FANNING BLAISE
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.

9. 发明公开

EP3140748A1 INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS 有权
标题翻译： VERBINDUNGSSYSTEME UND VERFAHREN MIT HYBRIDER MEMORY-CUBE-VERBINDUNGEN
公开(公告)号：EP3140748A1
公开(公告)日：2017-03-15
申请号：EP15789012.0
申请日：2015-05-01
申请人： Micron Technology, Inc.
发明人： LEIDEL, John D.
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F3/0607 , G06F3/0659 , G06F3/0685 , G06F13/1621 , G06F13/1657 , G06F13/1673 , G06F13/1684 , G06F13/40 , G06F13/4022 , G06F13/4234 , G06F2212/205 , G11C7/1075 , G11C21/00
摘要： System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
摘要翻译：片上系统（SoC）设备包括用于传送本地存储分组和系统互连分组的两个分组化存储器总线。在数据处理系统的原位配置中，两个或更多个SoC与一个或多个混合存储立方体（HMC）耦合。存储器分组使得能够与给定SoC的存储器域中的本地HMC进行通信。系统互连分组使得SoC之间的通信和存储器域之间的通信成为可能。在专用路由配置中，系统中的每个SoC都有自己的存储器域，以解决本地HMC和单独的系统互连域，以解决连接在系统互连域中的HMC集线器，HMC存储设备或其他SoC设备。

10. 发明公开

EP3011460A1 DEVICE, HOST APPARATUS, HOST SYSTEM, AND MEMORY SYSTEM 审中-公开
标题翻译：设备，主机设备，主机系统和存储系统
公开(公告)号：EP3011460A1
公开(公告)日：2016-04-27
申请号：EP14713935.6
申请日：2014-02-06
申请人： Kabushiki Kaisha Toshiba
发明人： FUJIMOTO, Akihisa , SAKAMOTO, Hiroyuki , MATSUKAWA, Shinichi
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F3/0622 , G06F3/0637 , G06F3/0679 , G06F13/16 , G06F13/4234
摘要： According to one embodiment, a device includes a semiconductor memory and a controller. The semiconductor memory includes first and second areas which are accessible from an outside. The controller controls the semiconductor memory. The device includes an unlocked state where reading from the first area and the second area is allowed, and a locked state where the reading from the first area is allowed and the reading from the second area is prohibited. The first area stores at least part of file system information. In the locked state, the at least part of the file system information is readable from the outside.

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