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1. 发明授权

EP3330861B1 PROCESSOR WITH MEMORY ARRAY OPERABLE AS EITHER VICTIM CACHE OR NEURAL NETWORK UNIT MEMORY 有权
公开(公告)号：EP3330861B1
公开(公告)日：2020-03-11
申请号：EP16205396.1
申请日：2016-12-20
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , REED, Douglas R
IPC分类号： G06F12/0811 , G06F12/0864 , G06F12/121 , G06N3/04 , G06N3/063

2. 发明公开

EP3316129A1 COMPILER SYSTEM FOR A PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 审中-公开
标题翻译：具有可扩展指令集体系结构的处理器的编译器系统，用于动态配置执行资源
公开(公告)号：EP3316129A1
公开(公告)日：2018-05-02
申请号：EP16207534.5
申请日：2016-12-30
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F9/45 , G06F15/78
CPC分类号： G06F8/41 , G06F8/443 , G06F8/4441 , G06F8/52 , G06F15/7867 , G06F15/7871 , G06F15/7892
摘要： A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for programming the PEU to perform the processing operation in response to the specified UDI. The compiler system includes a compiler that converts the application source program into the executable program, which includes an optimization routine that represents a portion of the application source program with the specified UDI and that inserts the UDI into the executable program, and that further inserts into the executable program a UDI load instruction that specifies the UDI and a location of the programming information in the executable program.
摘要翻译：一种编译器系统，根据通用处理器可执行的预定ISA将应用源程序转换为可执行程序。处理器包括一个可编程执行UDI的PEU。编译器系统包括PEU编程工具，其将要由处理器的PEU执行的处理操作的功能描述转换为用于编程PEU以执行处理操作以响应指定的UDI的编程信息。编译器系统包括一个将应用程序源程序转换为可执行程序的编译器，该程序包括一个优化例程，该例程表示具有指定UDI的应用程序源程序的一部分，并将UDI插入可执行程序中，并进一步插入可执行程序是UDI加载指令，其指定UDI和可执行程序中编程信息的位置。

3. 发明公开

EP3316146A1 PROCESSOR WITH PROGRAMMABLE PREFETCHER 有权
标题翻译：具有可编程预置器的处理器
公开(公告)号：EP3316146A1
公开(公告)日：2018-05-02
申请号：EP16207543.6
申请日：2016-12-30
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F12/0862 , G06F15/78
摘要： A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched load microinstructions and provides load requests to the memory system. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks the load requests. The prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The prefetch requester submits the at least one prefetch address to prefetch information from the memory system.
摘要翻译：一种处理器，包括前端，至少一个加载管线以及还包括用于预取来自外部存储器的信息的可编程预取器的存储器系统。前端将获取的程序指令转换为包含加载微指令的微指令并分派微指令以供执行。加载管道执行调度的加载微指令并向内存系统提供加载请求。可编程预取器包括负载监视器，可编程预取引擎和预取请求器。负载监视器跟踪加载请求。预取引擎被配置为由至少一个预取程序编程以作为编程的预取器来操作，使得在处理器的操作期间，编程的预取器基于由处理器发出的加载请求来生成至少一个预取地址。预取请求者提交至少一个预取地址以从存储器系统预取信息。

4. 发明公开

EP3330861A1 PROCESSOR WITH MEMORY ARRAY OPERABLE AS EITHER VICTIM CACHE OR NEURAL NETWORK UNIT MEMORY 有权
公开(公告)号：EP3330861A1
公开(公告)日：2018-06-06
申请号：EP16205396.1
申请日：2016-12-20
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , REED, Douglas R
IPC分类号： G06F12/0811 , G06F12/0864 , G06F12/121
摘要： A processor comprises a neural network unit (NNU) and a processing complex (PC) comprising a processing core and cache memory. The NNU comprises neural processing units (NPU), cache control logic (CCL) and a memory array (MA). To transition from a first mode in which the MA operates to hold neural network weights for the array of NPUs to a second mode in which the MA and CCL operate as a victim cache, the CCL begins to cache evicted cache lines into the MA in response to eviction requests and begins to provide to the PC lines that hit in the MA in response to load requests. To transition from the second mode to the first mode, the CCL invalidates all lines of the MA, ceases to cache evicted lines into the MA in response to eviction requests, and ceases to provide to the PC lines in response to load requests.

5. 发明公开

EP3232330A1 SANITIZE-AWARE DRAM CONTROLLER 有权
标题翻译： SANITIZE-AWARE DRAM控制器
公开(公告)号：EP3232330A1
公开(公告)日：2017-10-18
申请号：EP16203900.2
申请日：2016-12-13
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： PARKS, Terry , HOOKER, Rodney E , REED, Douglas R
IPC分类号： G06F12/0893 , G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0673 , G06F12/0893 , G06F13/1636 , G06F2212/1028 , G06F2212/1052 , G11C11/40611 , G11C11/40622 , G11C11/409 , Y02D10/13
摘要： A controller for controlling a dynamic random access memory (DRAM) comprising a plurality of blocks. A block is one or more units of storage in the DRAM for which the DRAM controller can selectively enable or disable refreshing. The DRAM controller includes flags each for association with a block of the blocks of the DRAM. A sanitize controller determines a block is to be sanitized and in response sets a flag associated with the block and disables refreshing the block. In response to subsequently receiving a request to read data from a location in the block, if the flag is clear, the DRAM controller reads the location and returns data read from it. If the flag is set, the DRAM controller refrains from reading the DRAM and returns a value of zero.
摘要翻译：一种用于控制包括多个块的动态随机存取存储器（DRAM）的控制器。块是DRAM中的一个或多个存储单元，DRAM控制器可以选择性地启用或禁用刷新。 DRAM控制器包括各自用于与DRAM的块的块相关联的标志。消毒控制器确定一个块将被消毒，并作为响应设置与该块关联的标志并禁止刷新该块。响应于随后接收到从块中的位置读取数据的请求，如果该标志清除，则DRAM控制器读取该位置并返回从其读取的数据。如果标志被设置，DRAM控制器不能读取DRAM并返回零值。

6. 发明授权

EP3316146B1 PROCESSOR WITH PROGRAMMABLE PREFETCHER 有权
公开(公告)号：EP3316146B1
公开(公告)日：2020-07-22
申请号：EP16207543.6
申请日：2016-12-30
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F12/0862 , G06F15/78

7. 发明授权

EP3179375B1 PROCESSOR WITH PROGRAMMABLE PREFETCHER 有权
公开(公告)号：EP3179375B1
公开(公告)日：2020-05-06
申请号：EP16203050.6
申请日：2016-12-08
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F12/0862 , G06F12/0897 , G06F15/78 , G06F9/38

8. 发明公开

EP3316130A1 CONVERSION SYSTEM FOR A PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 审中-公开
标题翻译：具有可扩展指令集架构的处理器的转换系统，用于动态配置执行资源
公开(公告)号：EP3316130A1
公开(公告)日：2018-05-02
申请号：EP16207539.4
申请日：2016-12-30
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F9/45 , G06F15/78
CPC分类号： G06F8/41 , G06F8/443 , G06F8/4441 , G06F8/52 , G06F15/7867 , G06F15/7871 , G06F15/7892
摘要： A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for the PEU to perform the processing operation in response to the UDI. A converter converts the standard executable program into the custom executable program and includes an optimization routine that replaces a portion of the standard executable program with the specified UDI and that inserts the UDI into the custom executable program, and that further inserts a UDI load instruction that specifies the UDI and a location of the programming information in the custom executable program.
摘要翻译：一种转换系统，其根据预定的ISA将标准可执行程序转换为可由通用处理器执行的定制可执行程序。处理器包括一个可编程执行UDI的PEU。转换系统包括PEU编程工具，其将要由处理器的PEU执行的处理操作的功能描述转换为用于PEU响应于UDI执行处理操作的编程信息。转换器将标准可执行程序转换为自定义可执行程序，并包含一个优化例程，该程序用指定的UDI替换标准可执行程序的一部分，并将UDI插入到自定义可执行程序中，并进一步插入UDI加载指令指定UDI和编程信息在自定义可执行程序中的位置。

9. 发明公开

EP3179375A1 PROCESSOR WITH PROGRAMMABLE PREFETCHER 有权
标题翻译：具有可编程预置器的处理器
公开(公告)号：EP3179375A1
公开(公告)日：2017-06-14
申请号：EP16203050.6
申请日：2016-12-08
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F12/0862 , G06F15/78
摘要： A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The requester uses each generated prefetch address to prefetch information from the external memory. A prefetch memory may store one or more prefetch programs and a prefetch programmer may be included to select from among stored prefetch programs to program the prefetcher based on an executing process. Each prefetch program may be configured according to a prefetch definition.
摘要翻译：包含可编程预取器的处理器，用于预取来自外部存储器的信息。可编程预取器包括负载监视器，可编程预取引擎和预取请求器。负载监视器跟踪处理器发出的加载请求，以从外部存储器中检索信息。可编程预取引擎被配置为由至少一个预取程序编程以作为编程预取器来操作，使得在处理器的操作期间，编程预取器基于由处理器发出的加载请求来生成至少一个预取地址。请求者使用每个生成的预取地址来预取来自外部存储器的信息。预取存储器可以存储一个或多个预取程序，并且可以包括预取编程器以从存储的预取程序中进行选择以基于执行过程对预取器进行编程。每个预取程序可以根据预取定义来配置。

10. 发明公开

EP3179362A1 PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 有权
标题翻译：可扩展指令集架构执行资源的动态配置处理器
公开(公告)号：EP3179362A1
公开(公告)日：2017-06-14
申请号：EP16203047.2
申请日：2016-12-08
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F9/30 , G06F15/78 , G06F9/22 , G06F9/28 , G06F9/45
CPC分类号： G06F9/3016 , G06F3/0604 , G06F3/0631 , G06F3/0673 , G06F8/41 , G06F8/443 , G06F8/447 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/30196 , G06F9/3836
摘要： A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.
摘要翻译：与处理器在可膨胀的指令集架构用于动态配置的执行资源。该处理器包括一个可编程执行单元（PEU）也可以被编程为响应于用户定义指令（UDI）执行用户定义的函数。所述PEU包括可编程逻辑元件和可编程互连器没有被共同编程以执行至少一个处理操作。甲UDI加载器是响应于UDI加载指令没有指定UDI和编程信息的位置也被用来将PEU编程。该PEU可以被编程为一个或多个过程的一个或多个UDIS。指令表存储每个UDI和相应的信息以识别UDI和可能重新编程PEU如果是必要的。甲UDI处理程序咨询指令表来识别所接收的UDI，并发送相应的信息到PEU执行对应的用户定义函数。

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