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1. 发明公开

EP3232330A1 SANITIZE-AWARE DRAM CONTROLLER 有权
标题翻译： SANITIZE-AWARE DRAM控制器
公开(公告)号：EP3232330A1
公开(公告)日：2017-10-18
申请号：EP16203900.2
申请日：2016-12-13
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： PARKS, Terry , HOOKER, Rodney E , REED, Douglas R
IPC分类号： G06F12/0893 , G11C11/406 , G11C11/4072
CPC分类号： G11C11/406 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0673 , G06F12/0893 , G06F13/1636 , G06F2212/1028 , G06F2212/1052 , G11C11/40611 , G11C11/40622 , G11C11/409 , Y02D10/13
摘要： A controller for controlling a dynamic random access memory (DRAM) comprising a plurality of blocks. A block is one or more units of storage in the DRAM for which the DRAM controller can selectively enable or disable refreshing. The DRAM controller includes flags each for association with a block of the blocks of the DRAM. A sanitize controller determines a block is to be sanitized and in response sets a flag associated with the block and disables refreshing the block. In response to subsequently receiving a request to read data from a location in the block, if the flag is clear, the DRAM controller reads the location and returns data read from it. If the flag is set, the DRAM controller refrains from reading the DRAM and returns a value of zero.
摘要翻译：一种用于控制包括多个块的动态随机存取存储器（DRAM）的控制器。块是DRAM中的一个或多个存储单元，DRAM控制器可以选择性地启用或禁用刷新。 DRAM控制器包括各自用于与DRAM的块的块相关联的标志。消毒控制器确定一个块将被消毒，并作为响应设置与该块关联的标志并禁止刷新该块。响应于随后接收到从块中的位置读取数据的请求，如果该标志清除，则DRAM控制器读取该位置并返回从其读取的数据。如果标志被设置，DRAM控制器不能读取DRAM并返回零值。

2. 发明公开

EP3153999A2 APPARATUS EMPLOYING USER-SPECIFIED BINARY POINT FIXED POINT ARITHMETIC 有权
标题翻译： VORRICHTUNG麻省理工大师冯BENUTZERSPEZIFISCHERBINÄRPUNKTFESTERPUNKTARITHMETIK
公开(公告)号：EP3153999A2
公开(公告)日：2017-04-12
申请号：EP16192951.8
申请日：2016-10-07
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G. Glenn , PARKS, Terry
IPC分类号： G06N3/063 , G06F9/00
摘要： An apparatus includes a plurality of arithmetic logic units each having an accumulator and an integer arithmetic unit that receives and performs integer arithmetic operations on integer inputs and accumulates integer results of a series of the integer arithmetic operations into the accumulator as an integer accumulated value. A register is programmable with an indication of a number of fractional bits of the integer accumulated values and an indication of a number of fractional bits of integer outputs. A first bit width of the accumulator is greater than twice a second bit width of the integer outputs. A plurality of adjustment units scale and saturate the first bit width integer accumulated values to generate the second bit width integer outputs based on the indications of the number of fractional bits of the integer accumulated values and outputs programmed into the register.
摘要翻译：一种装置包括多个具有累加器和整数运算单元的算术逻辑单元，该整数运算单元接收并对整数输入进行整数运算，并将一系列整数算术运算的整数结果累加到累加器中作为整数累积值。寄存器是可编程的，具有整数累加值的分数位数的指示和整数输出的分数位数的指示。累加器的第一位宽度大于整数输出的第二位宽度的两倍。多个调整单元对第一位宽整数累积值进行缩放和饱和，以基于整数累加值的分数位数和指令编程到寄存器中的指示来生成第二位宽整数输出。

3. 发明公开

EP3153998A2 NEURAL NETWORK UNIT THAT PERFORMS CONCURRENT LSTM CELL CALCULATIONS 有权
标题翻译： NEURONALE NETZWERKEINHEIT，DIE GLEICHZEITIGE LSTM-ZELLBERECHNUNGENAUSFÜHRT
公开(公告)号：EP3153998A2
公开(公告)日：2017-04-12
申请号：EP16192950.0
申请日：2016-10-07
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G. Glenn , PARKS, Terry , O'BRIEN, Kyle T.
IPC分类号： G06N3/063 , G06F9/00
CPC分类号： G06N3/063 , G06F7/483 , G06F9/00 , G06N3/04 , G06N3/0445
摘要： An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each of the N words. N processing units (PU) are arranged as N/J mutually exclusive PU groups. Each PU group has an associated OBWG. Each PU includes an accumulator and an arithmetic unit that performs operations on inputs, which include the accumulator output, to generate a first result for accumulation into the accumulator. Activation function units selectively perform an activation function on the accumulator outputs to generate results for provision to the N output buffer words. For each PU group, four of the J PUs and at least one of the activation function units compute an input gate, a forget gate, an output gate and a candidate state of a Long Short Term Memory (LSTM) cell, respectively, for writing to respective first, second, third and fourth words of the associated OBWG.
摘要翻译：输出缓冲器保持排列成N个字的N个字的每个N个字的N个字互斥输出缓冲器字组（OBWG）的N个字。 N个处理单元（PU）被布置为N / J个互斥PU组。每个PU组具有相关的OBWG。每个PU包括一个累加器和一个运算单元，对包含累加器输出的输入进行运算，以产生累加到累加器中的第一个结果。激活功能单元选择性地对累加器输出执行激活功能，以产生用于提供N个输出缓冲器字的结果。对于每个PU组，J PU中的四个和激活功能单元中的至少一个分别计算用于写入的长时间存储器（LSTM）单元的输入门，忘记门，输出门和候选状态到相关OBWG的第一，第二，第三和第四个字。

4. 发明公开

EP3153997A2 NEURAL NETWORK UNIT WITH OUTPUT BUFFER FEEDBACK AND MASKING CAPABILITY 有权
标题翻译：具有输出缓冲反馈和掩蔽能力的神经网络单元
公开(公告)号：EP3153997A2
公开(公告)日：2017-04-12
申请号：EP16192949.2
申请日：2016-10-07
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , PARKS, Terry , O'BRIEN, Kyle T.
IPC分类号： G06N3/063 , G06F9/00
CPC分类号： G06N3/063 , G06F9/00 , G06N3/0445
摘要： An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each. N processing units (PU) are arranged as N/J mutually exclusive PU groups each having an associated OBWG. Each PU has an accumulator, an arithmetic unit, and first and second multiplexed registers each having at least J+1 inputs and an output. A first input receives a memory operand and the other J inputs receive the J words of the associated OBWG. Each accumulator provides its output to a respective output buffer word. Each arithmetic unit performs an operation on the first and second multiplexed register outputs and the accumulator output to generate a result for accumulation into the accumulator. A mask input to the output buffer controls which words, if any, of the N words retain their current value or are updated with their respective accumulator output.
摘要翻译：输出缓冲器保存N个字，每个J字排列为N / J互斥输出缓冲器字组（OBWG）。 N个处理单元（PU）被布置为N / J互斥PU组，每个PU组具有关联的OBWG。每个PU具有累加器，算术单元以及第一和第二多路复用寄存器，每个寄存器至少具有J + 1个输入和一个输出。第一个输入接收内存操作数，其他J输入接收相关OBWG的J个字。每个累加器将其输出提供给相应的输出缓冲器字。每个算术单元对第一和第二多路复用寄存器输出和累加器输出执行操作，以产生累加到累加器的结果。输入到输出缓冲器的掩码控制N个字中的哪些字（如果有的话）保留它们的当前值或用它们各自的累加器输出更新。

5. 发明授权

EP3154000B1 NEURAL NETWORK UNIT WITH PLURALITY OF SELECTABLE OUTPUT FUNCTIONS 有权
公开(公告)号：EP3154000B1
公开(公告)日：2020-05-06
申请号：EP16192952.6
申请日：2016-10-07
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , PARKS, Terry
IPC分类号： G06N3/063 , G06F9/30

6. 发明授权

EP2997478B1 EFFICIENT ADDRESS TRANSLATION CACHING IN PROCESSOR THAT SUPPORTS LARGE NUMBER OF DIFFERENT ADDRESS SPACES 有权
公开(公告)号：EP2997478B1
公开(公告)日：2019-03-13
申请号：EP14891591.1
申请日：2014-11-26
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： PARKS, Terry , EDDY, Colin , MOHAN, Viswanath , BUNDA, John, D.
IPC分类号： G06F12/10 , G06F12/1027 , G06F12/109

7. 发明公开

EP3316146A1 PROCESSOR WITH PROGRAMMABLE PREFETCHER 有权
标题翻译：具有可编程预置器的处理器
公开(公告)号：EP3316146A1
公开(公告)日：2018-05-02
申请号：EP16207543.6
申请日：2016-12-30
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , HOOKER, Rodney E , PARKS, Terry , REED, Douglas R
IPC分类号： G06F12/0862 , G06F15/78
摘要： A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched load microinstructions and provides load requests to the memory system. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks the load requests. The prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The prefetch requester submits the at least one prefetch address to prefetch information from the memory system.
摘要翻译：一种处理器，包括前端，至少一个加载管线以及还包括用于预取来自外部存储器的信息的可编程预取器的存储器系统。前端将获取的程序指令转换为包含加载微指令的微指令并分派微指令以供执行。加载管道执行调度的加载微指令并向内存系统提供加载请求。可编程预取器包括负载监视器，可编程预取引擎和预取请求器。负载监视器跟踪加载请求。预取引擎被配置为由至少一个预取程序编程以作为编程的预取器来操作，使得在处理器的操作期间，编程的预取器基于由处理器发出的加载请求来生成至少一个预取地址。预取请求者提交至少一个预取地址以从存储器系统预取信息。

8. 发明授权

EP2972797B1 FRACTIONAL USE OF PREDICTION HISTORY STORAGE FOR OPERATING SYSTEM ROUTINES 有权
标题翻译：预测历史存储用于操作系统程序的分部使用
公开(公告)号：EP2972797B1
公开(公告)日：2018-04-04
申请号：EP14880052.7
申请日：2014-12-12
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HOOKER, Rodney, E. , PARKS, Terry , BUNDA, John, D.
IPC分类号： G06F9/38 , G06F9/44 , G06F9/46
CPC分类号： G06F9/46 , G06F9/3834 , G06F9/3838 , G06F9/3844 , G06F9/3851 , G06F9/4403
摘要： A microprocessor includes a predicting unit having storage for holding a prediction history of characteristics of instructions previously executed by the microprocessor. The predicting unit accumulates the prediction history and uses the prediction history to make predictions related to subsequent instruction executions. The storage comprises a plurality of portions separately controllable for accumulating the prediction history. The microprocessor also includes a control unit that detects the microprocessor is running an operating system routine and controls the predicting unit to use only a fraction of the plurality of portions of the storage to accumulate the prediction history while the microprocessor is running the operating system routine.

9. 发明公开

EP3153997A3 NEURAL NETWORK UNIT WITH OUTPUT BUFFER FEEDBACK AND MASKING CAPABILITY 有权
公开(公告)号：EP3153997A3
公开(公告)日：2017-06-28
申请号：EP16192949.2
申请日：2016-10-07
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , PARKS, Terry , O'BRIEN, Kyle T.
IPC分类号： G06N3/063 , G06N3/04 , G06F9/00
CPC分类号： G06N3/063 , G06F9/00 , G06N3/0445
摘要： An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each. N processing units (PU) are arranged as N/J mutually exclusive PU groups each having an associated OBWG. Each PU has an accumulator, an arithmetic unit, and first and second multiplexed registers each having at least J+1 inputs and an output. A first input receives a memory operand and the other J inputs receive the J words of the associated OBWG. Each accumulator provides its output to a respective output buffer word. Each arithmetic unit performs an operation on the first and second multiplexed register outputs and the accumulator output to generate a result for accumulation into the accumulator. A mask input to the output buffer controls which words, if any, of the N words retain their current value or are updated with their respective accumulator output.

10. 发明公开

EP3094004A1 HARDWARE DATA COMPRESSOR USING DYNAMIC HASH ALGORITHM BASED ON INPUT BLOCK TYPE 有权
标题翻译：硬糖尿病患者麻醉药物研究方法HASH-ALGORITHUSUS BASIEREND AUF EINGANGSBLOCKTYPEN
公开(公告)号：EP3094004A1
公开(公告)日：2016-11-16
申请号：EP15195323.9
申请日：2015-11-19
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： HENRY, G Glenn , PARKS, Terry
IPC分类号： H03M7/40 , H03M7/30
CPC分类号： H03M7/42 , H03M7/3086 , H03M7/6017 , H03M7/6088
摘要： A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block.
摘要翻译：一种硬件数据压缩器，其通过在输入块中较早地替换匹配字符串的后向指针来替换输入块中的字符串来压缩输入的字符块。哈希表用于搜索输入块中的匹配字符串。多个散列索引生成器各自对要替换的字符串的初始部分采用不同的哈希算法，以生成相应的索引。硬件数据压缩器还包括输入字符块的类型的指示。选择器根据输入块的类型选择由多个散列索引发生器之一生成的索引以索引到哈希表中。

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