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1. 发明授权

EP1100128B1 METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE 有权
标题翻译：法生产半导体器件
公开(公告)号：EP1100128B1
公开(公告)日：2009-04-15
申请号：EP99926834.5
申请日：1999-06-29
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , KAKIMOTO, Seizo , NAKANO, Masayuki LM Nara Yasuraginomichi 201 , ADACHI, Kouichiro
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device comprises a semiconductor substrate, isolation regions formed in the semiconductor substrate, a semiconductor layer of a first conductivity type formed between the isolation regions, a gate oxide layer formed on an active region of the semiconductor layer of the first conductivity type, a gate electrode formed on the gate oxide layer, an insulating layer formed on the sidewall of the gate electrode, and a semiconductor layer of a second conductivity type for source/drain formed adjacent to the insulating layer on the sidewall of the gate electrode and intended to cover part of the isolation regions. The gate electrode and the semiconductor layer of the first conductivity type are connected electrically, the semiconductor layer of the second conductivity type is formed above the semiconductor layer of the first conductivity type, and the thickness of the semiconductor layer of the second conductivity type is such that it gradually increases as the layer extends from the isolation region toward the gate electrode.

2. 发明公开

EP1335425A1 SEMICONDUCTOR DEVICE AND ITS PRODUCTION METHOD 审中-公开
标题翻译： HALBLEITERBAUEMENT在SEIN PRODUKTIONSVERFAHREN
公开(公告)号：EP1335425A1
公开(公告)日：2003-08-13
申请号：EP01976761.5
申请日：2001-10-19
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , SHIBATA, Akihide , KAKIMOTO, Seizo
IPC分类号： H01L21/8234 , H01L27/08 , H01L29/78 , H01L21/336 , H01L21/76 , H01L21/761
CPC分类号： H01L21/823481 , H01L21/761 , H01L21/76202 , H01L21/76232 , H01L21/823493
摘要： A semiconductor device having a two-layer well structure and a small margin required at the boundary of a well region and comprising a substrate-bias variable transistor and a DTMOS. Field effect transistors (223) are formed on a P-type shallow well region (212). The depth of a shallow device isolation region (214) on the P-type shallow well region (212) is less than the depth of the junction between an N-type deep well region (227) and the P-type shallow well region (212). Therefore the field effect transistors (223) share the P-type shallow well region (212). The P-type shallow well regions (212) independently of each other are easily formed since they are isolated from each other by a deep device isolation region (226) and the N-type deep well region (227).
摘要翻译：一种半导体器件，其具有在阱区的边界处所需的两层阱结构和小的边界，并且包括衬底偏置可变晶体管和DTMOS。场效应晶体管（223）形成在P型浅阱区（212）上。 P型浅井区域（212）上的浅装置隔离区域（214）的深度小于N型深井区域（227）和P型浅井区域（ 212）。因此，场效应晶体管（223）共享P型浅阱区（212）。彼此独立的P型浅阱区域（212）由于它们通过深度器件隔离区域（226）和N型深阱区域（227）彼此隔离而容易地形成。

3. 发明公开

EP2546900A1 LIGHT-EMITTING DEVICE MANUFACTURING METHOD, LIGHT-EMITTING DEVICE, LIGHTING DEVICE, BACKLIGHT, LIQUID-CRYSTAL PANEL, DISPLAY DEVICE, DISPLAY DEVICE MANUFACTURING METHOD, DISPLAY DEVICE DRIVE METHOD AND LIQUID-CRYSTAL DISPLAY DEVICE 无效
标题翻译：器具，用于产生一种发光器件，发光器件，照明装置，背光灯，液晶面板，显示设备制造方法的显示设备，方法，用于控制显示装置及液晶显示装置
公开(公告)号：EP2546900A1
公开(公告)日：2013-01-16
申请号：EP11753178.0
申请日：2011-02-22
申请人： Sharp Kabushiki Kaisha
发明人： NEGISHI, Tetsu , SHIBATA, Akihide , KOMIYA, Kenji , YOSHIOKA, Fumiyoshi , IWATA, Hiroshi , TAKAHASHI, Akira
IPC分类号： H01L33/62 , G02F1/13357 , H01L33/20
CPC分类号： G02F1/133603 , F21K9/00 , G02F1/133605 , G02F2001/133612 , G02F2001/133614 , G02F2001/133628 , H01L24/95 , H01L25/0753 , H01L33/06 , H01L33/18 , H01L33/20 , H01L33/38 , H01L33/62 , H01L2224/48091 , H01L2224/48227 , H01L2224/49107 , H01L2224/73265 , H01L2924/00013 , H01L2924/09701 , H01L2924/12036 , H01L2924/12041 , H01L2924/15787 , H01L2924/15788 , H01L2924/3025 , H01L2933/0041 , H01L2924/00 , H01L2924/00015 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A metal line 731 is formed in a linear area S of an insulative substrate 720, and moreover a metal line 732 is formed generally parallel to the metal line 731 with a specified distance thereto. The metal line 731 is connected to an n-type semiconductor core 701 of bar-like structure light-emitting elements 710A to 710D, and the metal line 732 is connected to a p-type semiconductor layer 702. By dividing the insulative substrate 720 into a plurality of divisional substrates, a plurality of light-emitting devices in each of which a plurality of bar-like structure light-emitting elements 710 are placed on the divisional substrates are formed. Out of a plurality of light-emitting elements, bar-like structure light-emitting elements 710 that, even if cut off in a substrate dividing step, have no influence on a desired light emission quantity, are placed in cutting areas of the insulative substrate 720. Thus, even if bar-like structure light-emitting elements 710 that have been broken by cutting do not emit light, light emission is fulfilled by the other uncut plural bar-like structure light-emitting elements.

4. 发明授权

EP0928021B1 PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：方法用于半导体元件
公开(公告)号：EP0928021B1
公开(公告)日：2007-06-13
申请号：EP98917666.4
申请日：1998-04-23
申请人： SHARP KABUSHIKI KAISHA
发明人： KATAOKA, Kotaro , IWATA, Hiroshi , NAKANO, Masayuki, Room 201 LM Nara Yasuraginomichi
IPC分类号： H01L21/336 , H01L29/78 , H01L21/28 , H01L21/285
CPC分类号： H01L21/02043 , H01L21/28052 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： A process for manufacturing a semiconductor device in which halogen atoms present on and in the surface of a silicon layer are partially removed to a concentration of 100 ppm or less and electrodes are formed on the resultant silicon layer, so that low-resistance electrodes can be formed and hence a highly reliable semiconductor device can be obtained.

5. 发明公开

EP0951071A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：EP0951071A1
公开(公告)日：1999-10-20
申请号：EP97913464.0
申请日：1997-11-27
申请人： SHARP KABUSHIKI KAISHA
发明人： IWATA, Hiroshi , KAKIMOTO, Seizou , NAKANO, Masayuki , MATSUOKA, Toshimasa
IPC分类号： H01L27/08
CPC分类号： H01L29/1087 , H01L27/092 , H01L29/7832
摘要： A semiconductor device which realizes a dynamic threshold operation based on the use of a bulk semiconductor substrate is provided. The semiconductor substrate comprises: a well region 11 of a first conductivity type; a source region 12 and a drain region 13 of a second conductivity type provided in the vicinity of the surface of the well region 11 of the first conductivity type; a channel region 14 provided between the regions 12 and 13 ; and a gate insulation film 15 and a gate electrode 16 deposited in this order on the channel region 14 , wherein the gate electrode 16 is connected to the well region 11 via a contact hole (not shown) in the gate insulation film 15 . In this transistor, the resistance of the well region 11 can be reduced by a factor of about ten to a hundred.
摘要翻译：提供了基于使用体半导体衬底实现动态阈值操作的半导体器件。该半导体衬底包括：第一导电类型的阱区域11; 设置在第一导电类型的阱区11的表面附近的第二导电类型的源极区12和漏极区13; 设置在区域12和13之间的沟道区域14; 以及在沟道区14上依次沉积的栅绝缘膜15和栅电极16，其中栅电极16经由栅绝缘膜15中的接触孔（未示出）连接到阱区11.在此晶体管，阱区11的电阻可以减少大约十倍到一百倍。

6. 发明公开

EP0928021A1 PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
标题翻译：方法用于半导体元件
公开(公告)号：EP0928021A1
公开(公告)日：1999-07-07
申请号：EP98917666.4
申请日：1998-04-23
申请人： SHARP KABUSHIKI KAISHA
发明人： KATAOKA, Kotaro , IWATA, Hiroshi , NAKANO, Masayuki, Room 201 LM Nara Yasuraginomichi
IPC分类号： H01L21/336 , H01L29/78 , H01L21/28
CPC分类号： H01L21/02043 , H01L21/28052 , H01L21/28512 , H01L21/28518 , H01L21/76897 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L2924/0002 , H01L2924/00
摘要： By removing halogen atoms existing on the surface of the silicon layer and in the subsurface thereof so that the concentration of halogen atoms becomes 100ppm or lower and forming an electrode on the resulting silicon layer, the electrode which has a low resistance can be produced, and a highly reliable semiconductor device can be produces as well.

7. 发明授权

EP0951071B1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：EP0951071B1
公开(公告)日：2009-02-04
申请号：EP97913464.0
申请日：1997-11-27
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , KAKIMOTO, Seizou , NAKANO, Masayuki , MATSUOKA, Toshimasa
IPC分类号： H01L27/092 , H01L27/02 , H01L29/786
CPC分类号： H01L29/1087 , H01L27/092 , H01L29/7832
摘要： A semiconductor device which materializes dynamic threshold operation, on the assumption of the application of a bulk semiconductor substrate. The semiconductor substrate has a first conductivity type well region (11), a source region (12) and a drain region (13) of second conductivity type are made in the vicinity of the surface of the first conductivity type of well region (11), a channel region (14) is provided between these regions (12 and 13), a gate insulating film (15) and a gate electrode (16) are stacked in order on the channel region (14), and the gate electrode (16) is connected to the well region (11) through the contact hole (not shown in the figure) of the gate insulating film (15). In this transistor, as compared with a conventional SOI substrate, the resistance of the well region (11) can be lowered to about one-tenth.
摘要翻译：假定应用体半导体衬底，实现动态阈值操作的半导体器件。在第一导电类型的阱区（11）的表面附近形成具有第一导电类型阱区（11），第二导电类型的源区（12）和漏区（13）的半导体衬底，在这些区域（12,13）之间设置沟道区域（14），在沟道区域（14）上依次层叠栅极绝缘膜（15）和栅极电极（16），栅极电极）通过栅极绝缘膜（15）的接触孔（图中未示出）连接到阱区（11）。在该晶体管中，与常规SOI衬底相比，阱区（11）的电阻可降至约十分之一。

8. 发明公开

EP1357598A1 SEMICONDUCTOR DEVICE AND PORTABLE ELECTRONIC DEVICE 审中-公开
标题翻译：哈巴克斯坦恐怖袭击事件
公开(公告)号：EP1357598A1
公开(公告)日：2003-10-29
申请号：EP01271852.4
申请日：2001-12-21
申请人： Sharp Kabushiki Kaisha
发明人： SHIBATA, Akihide , IWATA, Hiroshi , KAKIMOTO, Seizo
IPC分类号： H01L27/08 , H01L21/8234 , H01L27/088 , H01L21/76 , H01L21/761
CPC分类号： H01L27/0928 , H01L21/761 , H01L21/823878 , H01L21/823892
摘要： There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions (12) are formed in one P-type semiconductor substrate (11). The N-type deep well regions (12, 12) are electrically isolated by the P-type semiconductor substrate (11). Over the N-type deep well regions (12), a P-type deep well region (13) and a P-type shallow well region (15) are formed to fabricate an N-type substrate variable-bias transistor (26). Over the N-type deep well region (12), an N-type shallow well region (14) is formed to fabricate a P-type substrate variable-bias transistor (25). Further a P-type DTMOS (28) and an N-type DTMOD (27) are fabricated.
摘要翻译：提供了包括DTMOS和基板可变偏置晶体管的半导体器件以及可以以降低的功耗进行操作的便携式电子设备。在一个P型半导体衬底（11）中形成N型深阱区（12）。 N型深阱区域（12,12）由P型半导体衬底（11）电隔离。在N型深阱区域（12）上形成有P型深阱区域（13）和P型浅阱区域（15），以制造N型衬底可变偏压晶体管（26）。在N型深井区域（12）上形成有N型浅井区域（14），以制造P型衬底可变偏压晶体管（25）。此外，还制作了P型DTMOS（28）和N型DTMOD（27）。

9. 发明公开

EP1343207A1 SEMICONDUCTOR DEVICE AND PORTABLE ELECTRONIC APPARATUS 有权
标题翻译： HALBLEITERBAUEMENT UND TRAGBARE ELEKTRONISCHE VORRICHTUNG
公开(公告)号：EP1343207A1
公开(公告)日：2003-09-10
申请号：EP01982765.8
申请日：2001-11-13
申请人： Sharp Kabushiki Kaisha
发明人： SHIBATA, Akihide , IWATA, Hiroshi , KAKIMOTO, Seizo
IPC分类号： H01L27/08 , H01L27/085 , H01L27/092 , G06F17/60
CPC分类号： H01L21/76229 , H01L21/823892 , H01L27/092 , H01L27/0921
摘要： There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.
摘要翻译：提供了具有DTMOS和衬底偏置可变晶体管的低功耗和高可靠性的半导体器件，以及使用该半导体器件的便携式电子设备。在半导体衬底（11）上，形成三层阱区域（12,14,16,13,15,16），并且在所述半导体衬底（11）上设置DTMOS（29,30）和衬底偏置可变晶体管（27,28）浅井区（16,17）。在形成PNP，NPN或NPNP结构的边界处提供大宽度器件隔离区（181,182,183），其中在两侧的阱区具有相同的条件下提供小宽度器件隔离区（18）导电型。因此，可以使提供单独导电类型的衬底偏置可变晶体管（27,28）的各种导电类型的多个阱区彼此电独立，从而降低功耗。此外，可以抑制闩锁现象。

10. 发明公开

EP1246258A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURE THEREOF, AND INFORMATION PROCESSING DEVICE 有权
标题翻译： HALBLEITERANORDNUNG UND INFORMATIONSVERARBEITUNGSANORDNUNG
公开(公告)号：EP1246258A1
公开(公告)日：2002-10-02
申请号：EP00986014.9
申请日：2000-12-28
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , SHIBATA, Akihide , KAKIMOTO, Seizo , ADACHI, Kouichiro , NAKANO, Masayuki LM Narayasuraginomichi 201
IPC分类号： H01L29/78
CPC分类号： H01L29/66628 , H01L21/2251 , H01L21/823814 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/665 , H01L29/66545 , H01L29/7834 , H01L29/78657
摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103 , part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105 , and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105 . At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A' . An angle between the second surface and a surface of the isolation region is 80 degrees or less.
摘要翻译：半导体器件1910包括半导体衬底100，其包括隔离区域101和有源区域102，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。第二表面相对于第一表面A-A'倾斜。第二表面与隔离区域的表面之间的角度为80度以下。

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