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1. 发明授权

EP1100128B1 METHOD OF MANUFACTURE OF A SEMICONDUCTOR DEVICE 有权
标题翻译：法生产半导体器件
公开(公告)号：EP1100128B1
公开(公告)日：2009-04-15
申请号：EP99926834.5
申请日：1999-06-29
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , KAKIMOTO, Seizo , NAKANO, Masayuki LM Nara Yasuraginomichi 201 , ADACHI, Kouichiro
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device comprises a semiconductor substrate, isolation regions formed in the semiconductor substrate, a semiconductor layer of a first conductivity type formed between the isolation regions, a gate oxide layer formed on an active region of the semiconductor layer of the first conductivity type, a gate electrode formed on the gate oxide layer, an insulating layer formed on the sidewall of the gate electrode, and a semiconductor layer of a second conductivity type for source/drain formed adjacent to the insulating layer on the sidewall of the gate electrode and intended to cover part of the isolation regions. The gate electrode and the semiconductor layer of the first conductivity type are connected electrically, the semiconductor layer of the second conductivity type is formed above the semiconductor layer of the first conductivity type, and the thickness of the semiconductor layer of the second conductivity type is such that it gradually increases as the layer extends from the isolation region toward the gate electrode.

2. 发明公开

EP1100128A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译： VERFAHREN ZUR HERSTELLUNG EINER HALBLEITERANORDNUNG
公开(公告)号：EP1100128A1
公开(公告)日：2001-05-16
申请号：EP99926834.5
申请日：1999-06-29
申请人： Sharp Kabushiki Kaisha
发明人： IWATA, Hiroshi , KAKIMOTO, Seizo , NAKANO, Masayuki LM Nara Yasuraginomichi 201 , ADACHI, Kouichiro
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/783 , H01L21/84 , H01L29/66628 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78654
摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.
摘要翻译：根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅极侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖相应器件隔离区的一部分的第二导电类型半导体层，第二导电类型半导体层用作源区和/或漏区。栅电极和第一导电型半导体层彼此电连接。第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。

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