专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1065627A2 Non-contact type ic card and process for manufacture 审中-公开
标题翻译： Kontaktlose IC-Karte und Herstellungsverfahren
公开(公告)号：EP1065627A2
公开(公告)日：2001-01-03
申请号：EP00305371.7
申请日：2000-06-26
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Higuchi, Tsutomu , Fujii, Tomoharu , Okamura, Shigeru , Sato, Tsuyoshi , Wakabayashi, Takayoshi , Akagawa, Masatoshi
IPC分类号： G06K19/077
CPC分类号： G06K19/0775 , G06K19/07749 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/16225 , H01L2224/16227 , H01L2224/81395 , H01L2924/00014
摘要： An IC card comprises: a plane coil (52) having respective terminal sections (52a); a semiconductor element (54) arranged at a position not overlapping with the plane coil (52), the semiconductor element (54) having electrode terminals (56); means (18) for electrically connecting the respective terminal sections (52a) of the plane coil (52) to the electrode terminals (56) of the semiconductor element (54); and a reinforcing frame (12) arranged on a face substantially the same as that of the semiconductor element (54) so that the semiconductor element (54) is surrounded by the reinforcing frame (12).
摘要翻译： IC卡包括：具有相应端子部分（52a）的平面线圈（52）; 半导体元件（54），布置在与所述平面线圈（52）不重叠的位置处，所述半导体元件（54）具有电极端子（56）; 用于将平面线圈（52）的各个端子部分（52a）电连接到半导体元件（54）的电极端子（56）的装置（18）; 以及布置在与半导体元件（54）基本相同的表面上的加强框架（12），使得半导体元件（54）被加强框架（12）包围。

2. 发明公开

EP0734059A3 Chip sized semiconductor device and a process for making it 失效
标题翻译： Halbleitervorrichtung mit Chipabmessungen und Herstellungsverfahren
公开(公告)号：EP0734059A3
公开(公告)日：1997-08-13
申请号：EP96301936.9
申请日：1996-03-21
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi , Higashi, Mitsutoshi , Iizuka, Hajime , Arai, Takehiro
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L24/12 , H01L23/3107 , H01L23/3114 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L23/552 , H01L24/02 , H01L24/05 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/1134 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13144 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/19041 , H01L2924/3025 , H01L2924/00015 , H01L2224/13099 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A process for making a chip sized semiconductor device (30), in which a semiconductor chip (32) is prepared so as to have electrodes on one surfaces thereof and an electrically insulating passivation film (34) formed on the one surface except for areas where the electrodes (36) exist. An insulation sheet (38) is prepared so as to have first and second surfaces and a metallic film (60) coated on the first surface. The second surface of the insulation sheet (38) is adhered on the semiconductor chip (32). First via-holes (39) are provided in the metallic film (40) at positions corresponding to the electrodes (36). Second via-holes (39) are provided in the insulation sheet (38) at positions corresponding to the first via-holes (39) so that the electrodes (36) are exposed. The metallic film (40) is electrically connected to the electrodes (36) of the semiconductor chip (32) through the first and second via-holes (39). A circuit pattern (40) is formed from the metallic film so that the circuit pattern (40) has external terminal connecting portions (43). An insulation film (42) is adhered on the insulation sheet (38) so that the external terminal connecting portions (43) are exposed. External connecting terminals (46) are electrically connected to the external terminal connecting portions (43) of the circuit pattern (40).
摘要翻译：一种制造芯片尺寸的半导体器件（30）的工艺，其中制备半导体芯片（32）以在其一个表面上具有电极，以及形成在一个表面上的电绝缘钝化膜（34），除了存在电极（36）。制备绝缘片（38）以具有第一表面和第二表面以及涂覆在第一表面上的金属膜（60）。绝缘片（38）的第二表面粘附在半导体芯片（32）上。在与电极（36）相对应的位置处，金属膜（40）中设置有第一通孔（39）。第二通孔（39）在与第一通孔（39）相对应的位置处设置在绝缘片（38）中，以使电极（36）露出。金属膜（40）通过第一和第二通孔（39）与半导体芯片（32）的电极（36）电连接。电路图案（40）由金属膜形成，使得电路图案（40）具有外部端子连接部分（43）。绝缘膜（42）粘附在绝缘片（38）上，使得外部端子连接部分（43）露出。外部连接端子（46）电连接到电路图案（40）的外部端子连接部分（43）。

3. 发明公开

EP1381080A2 Component-embedded board fabrication method and apparatus 审中-公开
标题翻译：。。。。。。。。。。。。。。。。。。
公开(公告)号：EP1381080A2
公开(公告)日：2004-01-14
申请号：EP03015264.9
申请日：2003-07-07
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi , Sekigawa, Kazunari , Wakabayashi, Shinichi
IPC分类号： H01L21/60
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/24011 , H01L2224/2402 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/8203 , H01L2224/82102 , H01L2224/92244 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01056 , H01L2924/01073 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/185 , Y10T29/49004 , Y10T29/49117 , Y10T29/49126 , Y10T29/49131 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/53061 , Y10T29/53087 , Y10T29/53174 , Y10T29/532 , H01L2224/82 , H01L2924/00
摘要： An apparatus 1 for fabricating a component-embedded board according to the present invention comprises: a detecting unit 11 for detecting, before the board 21 is covered with an insulating layer 23, the actual position of an electronic component 22 formed on the surface of the board 21; a holding unit 12 for calculating a displacement between the design position of the electronic component 22 and the actual position of the electronic component 22 on the surface of the board 21, and for holding the displacement as displacement data; and a correcting unit 13 for correcting, based on the displacement data, design data to be used for processing the board 21 after the board 21 is covered with the insulating layer 23.
摘要翻译：根据本发明的用于制造部件嵌入式基板的装置1包括：检测单元11，用于在板21被绝缘层23覆盖之前检测形成在绝缘层23的表面上的电子部件22的实际位置板21; 用于计算电子部件22的设计位置与电子部件22在电路板21的表面上的实际位置之间的位移并将位移保持为位移数据的保持单元12; 以及校正单元13，用于基于位移数据，校正板21被绝缘层23覆盖之后用于处理板21的设计数据。图像

4. 发明授权

EP0734065B1 Chip sized semiconductor device and multi-chip-sized semiconductor device 失效
标题翻译：一种半导体器件，如在一个或多个芯片的尺寸
公开(公告)号：EP0734065B1
公开(公告)日：2002-06-19
申请号：EP96301937.7
申请日：1996-03-21
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi
IPC分类号： H01L23/532 , H01L23/498
CPC分类号： H01L23/5328 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13164 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/014 , H01L2924/00014 , H01L2224/13099 , H01L2924/00

5. 发明公开

EP0734065A2 Chip sized semiconductor device 失效
标题翻译：在芯片尺寸的半导体器件
公开(公告)号：EP0734065A2
公开(公告)日：1996-09-25
申请号：EP96301937.7
申请日：1996-03-21
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi
IPC分类号： H01L23/532
CPC分类号： H01L23/5328 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13164 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/014 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A chip sized semiconductor device (30) includes a semiconductor chip (32) having upper and lower surfaces. The chip (32) has electrodes (36) formed on its upper surface. An electrically insulating passivation film (34) is formed on the upper surface of the semiconductor chip (32) except for areas where the electrodes (36) exist. An anisotropic conductive sheet (38) has an upper surface provided with a circuit pattern (40) formed on it and a second surface adhered to the passivation film (34). The circuit pattern (40) has inner and outer connecting portions. An electrically insulating film (42) covers the upper surface of the anisotropic conductive sheet (38) so that the outer connecting portions of the circuit pattern (40) are exposed to be connected to external connecting terminals (46). The anisotropic conductive sheet (38) is partially pressed at positions corresponding to the electrodes (36), so that the inner portions of the circuit pattern (40) are thereby electrically connected to said electrodes (36) of the semiconductor chip (32).

6. 发明授权

EP0734059B1 Chip sized semiconductor device and a process for making it 失效
标题翻译：与芯片尺寸和制造工艺的半导体器件
公开(公告)号：EP0734059B1
公开(公告)日：2005-11-09
申请号：EP96301936.9
申请日：1996-03-21
申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.
发明人： Akagawa, Masatoshi , Higashi, Mitsutoshi , Iizuka, Hajime , Arai, Takehiro
IPC分类号： H01L21/768 , H01L23/528 , H01L23/485
CPC分类号： H01L24/12 , H01L23/3107 , H01L23/3114 , H01L23/5283 , H01L23/5329 , H01L23/53295 , H01L23/552 , H01L24/02 , H01L24/05 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05008 , H01L2224/05548 , H01L2224/05569 , H01L2224/05572 , H01L2224/1134 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13144 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/19041 , H01L2924/3025 , H01L2924/00015 , H01L2224/13099 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： A process for making a chip sized semiconductor device (30), in which a semiconductor chip (32) is prepared so as to have electrodes on one surfaces thereof and an electrically insulating passivation film (34) formed on the one surface except for areas where the electrodes (36) exist. An insulation sheet (38) is prepared so as to have first and second surfaces and a metallic film (60) coated on the first surface. The second surface of the insulation sheet (38) is adhered on the semiconductor chip (32). First via-holes (39) are provided in the metallic film (40) at positions corresponding to the electrodes (36). Second via-holes (39) are provided in the insulation sheet (38) at positions corresponding to the first via-holes (39) so that the electrodes (36) are exposed. The metallic film (40) is electrically connected to the electrodes (36) of the semiconductor chip (32) through the first and second via-holes (39). A circuit pattern (40) is formed from the metallic film so that the circuit pattern (40) has external terminal connecting portions (43). An insulation film (42) is adhered on the insulation sheet (38) so that the external terminal connecting portions (43) are exposed. External connecting terminals (46) are electrically connected to the external terminal connecting portions (43) of the circuit pattern (40).

7. 发明公开

EP1381080A3 Component-embedded board fabrication method and apparatus 审中-公开
标题翻译：嵌入式组件及其制备方法局
公开(公告)号：EP1381080A3
公开(公告)日：2005-08-03
申请号：EP03015264.9
申请日：2003-07-07
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi , Sekigawa, Kazunari , Wakabayashi, Shinichi
IPC分类号： H01L21/60
CPC分类号： H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/24011 , H01L2224/2402 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/8203 , H01L2224/82102 , H01L2224/92244 , H01L2224/97 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01039 , H01L2924/01056 , H01L2924/01073 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/185 , Y10T29/49004 , Y10T29/49117 , Y10T29/49126 , Y10T29/49131 , Y10T29/49146 , Y10T29/49155 , Y10T29/49165 , Y10T29/53061 , Y10T29/53087 , Y10T29/53174 , Y10T29/532 , H01L2224/82 , H01L2924/00
摘要： An apparatus 1 for fabricating a component-embedded board according to the present invention comprises: a detecting unit 11 for detecting, before the board 21 is covered with an insulating layer 23, the actual position of an electronic component 22 formed on the surface of the board 21; a holding unit 12 for calculating a displacement between the design position of the electronic component 22 and the actual position of the electronic component 22 on the surface of the board 21, and for holding the displacement as displacement data; and a correcting unit 13 for correcting, based on the displacement data, design data to be used for processing the board 21 after the board 21 is covered with the insulating layer 23.

8. 发明公开

EP1065627A3 Non-contact type ic card and process for manufacture 审中-公开
标题翻译：非接触式IC卡和制造工艺
公开(公告)号：EP1065627A3
公开(公告)日：2003-01-02
申请号：EP00305371.7
申请日：2000-06-26
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Higuchi, Tsutomu , Fujii, Tomoharu , Okamura, Shigeru , Sato, Tsuyoshi , Wakabayashi, Takayoshi , Akagawa, Masatoshi
IPC分类号： G06K19/077
CPC分类号： G06K19/0775 , G06K19/07749 , H01L2224/05571 , H01L2224/05573 , H01L2224/05644 , H01L2224/16225 , H01L2224/16227 , H01L2224/81395 , H01L2924/00014
摘要： An IC card comprises: a plane coil (52) having respective terminal sections (52a); a semiconductor element (54) arranged at a position not overlapping with the plane coil (52), the semiconductor element (54) having electrode terminals (56); means (18) for electrically connecting the respective terminal sections (52a) of the plane coil (52) to the electrode terminals (56) of the semiconductor element (54); and a reinforcing frame (12) arranged on a face substantially the same as that of the semiconductor element (54) so that the semiconductor element (54) is surrounded by the reinforcing frame (12).

9. 发明公开

EP1471570A1 Method of mounting an electronic part on a mounting board 审中-公开
标题翻译： Methode zum Aufsetzen eines elektronisches Teils auf eine Montageplatte
公开(公告)号：EP1471570A1
公开(公告)日：2004-10-27
申请号：EP04009746.1
申请日：2004-04-23
申请人： Suga, Tadatomo , Shinko Electric Industries Co., Ltd. , Oki Electric Industry Co., Ltd. , Sharp Kabushiki Kaisha , Sony Corporation , Kabushiki Kaisha Toshiba , NEC CORPORATION , Hitachi, Ltd. , FUJITSU LIMITED , MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. , MITSUBISHI DENKI KABUSHIKI KAISHA , Rohm Co., Ltd.
发明人： Suga, Tadatomo , Itoh, Toshihiro , Nakazawa, Hideto , Akagawa, Masatoshi
IPC分类号： H01L21/60 , H01L21/603 , H01L23/485 , H01L21/56 , H01L21/48 , H01L23/538 , H01L21/00
CPC分类号： H01L24/81 , H01L23/49816 , H01L2224/05568 , H01L2224/05573 , H01L2224/13111 , H01L2224/13144 , H01L2224/16 , H01L2224/81054 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H05K3/3436 , H05K2203/085 , H05K2203/086 , Y02P70/613 , Y10T29/4913 , Y10T29/49144 , Y10T29/49149 , Y10T29/49197 , H01L2224/05624 , H01L2924/00014
摘要： A method of mounting an electronic part on a board, in which an electronic part and a mounting board on which the electronic part is to be mounted are placed in a vacuum or inert atmosphere, and the electronic part is mounted on the board by bringing the bonding members of the electronic part and the board into contact with each other at normal temperature to thereby mount the electronic part on the board, the method comprising forming the bonding members of at least one of the electronic part and the board out of a solder material, and bringing the bonding members of the electronic part and the board into contact with each other without preprocessing the bonding surfaces of the bonding members.
摘要翻译：具有焊锡凸块（13）的封装（11）和具有由焊料材料制成的焊盘（17）的布线板（15）放置在真空或惰性气氛中，使凸块与相应的焊盘接触，而无需预处理在正常温度下接合凸块和接合焊盘的表面以进行接合。

10. 发明公开

EP0734065A3 Chip sized semiconductor device 失效
标题翻译：在Chipgrösse的Halbleiteranordnung
公开(公告)号：EP0734065A3
公开(公告)日：1997-03-05
申请号：EP96301937.7
申请日：1996-03-21
申请人： SHINKO ELECTRIC INDUSTRIES CO. LTD.
发明人： Akagawa, Masatoshi
IPC分类号： H01L23/532
CPC分类号： H01L23/5328 , H01L2224/1134 , H01L2224/131 , H01L2224/13144 , H01L2224/13164 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2924/00013 , H01L2924/014 , H01L2924/00014 , H01L2224/13099 , H01L2924/00
摘要： A chip sized semiconductor device (30) includes a semiconductor chip (32) having upper and lower surfaces. The chip (32) has electrodes (36) formed on its upper surface. An electrically insulating passivation film (34) is formed on the upper surface of the semiconductor chip (32) except for areas where the electrodes (36) exist. An anisotropic conductive sheet (38) has an upper surface provided with a circuit pattern (40) formed on it and a second surface adhered to the passivation film (34). The circuit pattern (40) has inner and outer connecting portions. An electrically insulating film (42) covers the upper surface of the anisotropic conductive sheet (38) so that the outer connecting portions of the circuit pattern (40) are exposed to be connected to external connecting terminals (46). The anisotropic conductive sheet (38) is partially pressed at positions corresponding to the electrodes (36), so that the inner portions of the circuit pattern (40) are thereby electrically connected to said electrodes (36) of the semiconductor chip (32).
摘要翻译：芯片尺寸的半导体器件（30）包括具有上表面和下表面的半导体芯片（32）。芯片（32）具有形成在其上表面上的电极（36）。除了存在电极（36）的区域之外，在半导体芯片（32）的上表面上形成电绝缘钝化膜（34）。各向异性导电片（38）具有设置有形成在其上的电路图案（40）的上表面和粘附到钝化膜（34）的第二表面。电路图案（40）具有内部和外部连接部分。电绝缘膜（42）覆盖各向异性导电片（38）的上表面，使得电路图案（40）的外部连接部分暴露以连接到外部连接端子（46）。各向异性导电片（38）被部分地压在与电极（36）对应的位置处，使得电路图案（40）的内部部分电连接到半导体芯片（32）的所述电极（36）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式