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    • 10. 发明授权
    • MULTI-SAMPLING SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER
    • 多采样SIGMA-DELTA模拟数字转换器
    • EP1374410B1
    • 2006-10-25
    • EP01973125.6
    • 2001-09-18
    • QUALCOMM INCORPORATED
    • BAZARJANI, Seyfollah
    • H03M3/02
    • H03M3/47H03M3/406H03M3/418H03M3/43H03M3/454
    • A bandpass SIGMA DELTA ADC utilizing either a single-loop or a MASH architecure wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, a two-path interleaved resonator, or a four-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a SIGMA DELTA ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 SIGMA DELTA ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass SIGMA DELTA ADC can also be used in conjunction with undersampling to provide a frequency downconversion.
    • 使用单环或MASH架构的带通SIGMA DELTA ADC,其中谐振器被实现为延迟单元谐振器,基于延迟单元的谐振器,正向 - 欧拉谐振器,双路交叉谐振器或四路谐振器, 路径交错谐振器。 谐振器可以用模拟电路技术(如有源RC,gm-C,MOSFET-C,开关电容或开关电流)合成。 开关电容或开关电流电路可以使用单采样,双采样或多采样电路进行设计。 使用开关电容电路的SIGMA DELTA ADC的非严格要求允许ADC在CMOS工艺中实现,以最大限度地降低成本并降低功耗。 双采样电路提供了改进的匹配和提高了采样时钟抖动的容限。 特别是,带通MASH 4-4 SIGMA DELTA ADC在CDMA应用中以32的过采样比率提供85 dB的模拟信噪比。 带通SIGMA DELTA ADC也可以与欠采样一起使用以提供频率下变频。