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1. 发明公开

EP2523354A1 Digital receiver and method 失效转让
标题翻译： Digitalempfängerund Verfahren
公开(公告)号：EP2523354A1
公开(公告)日：2012-11-14
申请号：EP12157021.2
申请日：2004-03-31
申请人： Nortel Networks Ltd.
发明人： Morris, Bradley J. , Fuller, Arthur T. G.
IPC分类号： H04B1/28 , H03M3/02
CPC分类号： H04L27/22 , H03M3/462 , H03M3/47 , H03M7/3028 , H04B1/0007
摘要： A receiver and method is provided for sigma-delta converting an RF signal to a digital signal and downconverting to a digital baseband signal. The RF signal is split into N phases, as can be accomplished using a sample and hold circuit, and each phase is digitized, as can be accomplished using an analog-to-digital (A/D) sigma-delta converter. Polyphase decimation techniques and demodulation are applied to the phased signals to generate a demodulated digital signal. The demodulated digital signal is further downconverted to the appropriate baseband signal.
摘要翻译：提供了一种接收机和方法，用于将RF信号转换成数字信号并下变频到数字基带信号的Σ-Δ。 RF信号被分为N个相位，可以使用采样和保持电路来实现，并且每个相位被数字化，如可以使用模数（A / D）Σ-Δ转换器来实现的。将多相抽取技术和解调应用于相控信号以产生解调数字信号。解调的数字信号进一步下变频到适当的基带信号。

2. 发明公开

EP1401105A1 Voltage offset compensation method for time-interleaved multi-path analog-to-digital sigma-delta converters and respective circuit 有权
标题翻译： Offsetspannungskompensationsverfahrenfürparallele zeitverschachtelte Analog-Digitalwandler sowie Schaltungdafür
公开(公告)号：EP1401105A1
公开(公告)日：2004-03-24
申请号：EP02425563.0
申请日：2002-09-17
申请人： Siemens Mobile Communications S.p.A.
发明人： Gatti, Umberto , Malcovati, Piero , Ferragina, Vincenzo , Fornasari, Andrea
IPC分类号： H03M1/10
CPC分类号： H03M3/384 , H03M3/47
摘要： A multi-path time-interleaved analog-to-digital converter (MP-ADC) exploits an additional reference ADC cyclically connected in parallel to each ADC component part to be calibrated of the multi-path ADC, which can be of any kind, in particular sigma-delta, to whom conventional calibration techniques cannot be applied because of its stochastic behaviour. For each ADC component part the algebraic differences between successive digital outputs of the reference ADC and the ADC under calibration are forwarded to an accumulator circuit (13) which integrates them over a given time slot, obtaining a digital word (CH1',...,CH4') proportional to the difference between the offset of the two paths. A digital adder adds up the digital word so obtained to the output of the ADC component part under calibration multiplied by a scale factor which depends on the length of the given time slot. After a reasonable time the voltage offset of each individual path is proportional to the voltage offset of the only reference path, not necessarily zero. Optionally, the outputs of the digital adder are de-scaled by the same scale factor, restoring the original value. The time-interleaved ADC is continuously running and the voltage offset calibration is performed in background without affecting the normal operation (fig.7) .
摘要翻译：多路时间交织的模数转换器（MP-ADC）利用了一个额外的参考ADC，并行地并行地与待校准的多路径ADC的每个ADC组件部分并行地进行校准，该多路径ADC可以是任何类型的，特定的Σ-Δ，由于其随机行为，传统的校准技术不能应用于此。对于每个ADC组件部分，参考ADC和ADC在校准之间的连续数字输出之间的代数差异被转发到累加器电路（13），其在给定时隙上对它们进行积分，获得数字字（CH1'，...），CH4'）与两个路径的偏移之间的差成比例。数字加法器将所获得的数字字相加在校准下的ADC分量部分的输出乘以比例因子，该比例因子取决于给定时隙的长度。在合理的时间之后，每个单独路径的电压偏移量与唯一参考路径的电压偏移成比例，不一定为零。可选地，数字加法器的输出通过相同的比例因子进行缩放，恢复原始值。时间交织的ADC连续运行，并且在背景中执行电压偏移校准，而不影响正常操作（图7）。

3. 发明公开

EP1195019A4 DIRECT CONVERSION DELTA-SIGMA RECEIVER 审中-公开
标题翻译：与直接执行DELTA-SIGMA接收机
公开(公告)号：EP1195019A4
公开(公告)日：2002-09-04
申请号：EP00943000
申请日：2000-06-20
申请人： DITRANS CORP
发明人： MASENTEN WESLEY K , HICKLING RONALD M
IPC分类号： H03M3/00 , H04B14/06 , H03M3/02 , H04B1/28 , H04L27/233
CPC分类号： H04B14/062 , H03M3/40 , H03M3/43 , H03M3/456 , H03M3/47
摘要： A wireless receiver receives a wireless signal by inverting the polarity (78) of an incoming waveform on every one half clock cycle of a conversion clock to produce a commutated waveform and converting said commutated waveform to a series of representative digital values using a delta-sigma modulator (80, 82, 84, 86) clocked by the conversion clock. In this way, the receiver operates over a large dynamic range and the use of automatic gain control in the front end may be eliminated.

4. 发明授权

EP0734125B1 Delta sigma analog-to-digital converter 失效
标题翻译：经过Delta-Sigma模数转换器Digitalwandler
公开(公告)号：EP0734125B1
公开(公告)日：2002-04-03
申请号：EP96300211.8
申请日：1996-01-11
申请人： LECROY CORPORATION
发明人： Cake, Brian V. , Goumaz, Jean-Francois , LeCroy, Walter O.
IPC分类号： H03M3/02
CPC分类号： H03M3/47 , H03M3/43 , H03M3/456

5. 发明公开

EP1164702A2 Method of performing A/D conversion, and an A/D converter 审中-公开
标题翻译：维也纳祖尔A / D-Wandlung和A / D-Wandler
公开(公告)号：EP1164702A2
公开(公告)日：2001-12-19
申请号：EP01000207.9
申请日：2001-06-12
申请人： NOKIA MOBILE PHONES LTD.
发明人： Aunio, Antti
IPC分类号： H03M3/02
CPC分类号： H03M3/47 , H03M3/418
摘要： The invention relates to a method of performing AID conversion and to an A/D converter. The A/D conversion is performed by using at least two sigma-delta converters (50, 52) connected in cascade, the sigma-delta converters (50, 52) operating at a double sampling rate.
摘要翻译：本发明涉及一种执行AID转换和A / D转换器的方法。 A / D转换通过使用串联连接的至少两个Σ-Δ转换器（50,52）来执行，Σ-Δ转换器（50,52）以双倍采样率工作。

6. 发明公开

EP2658131A1 Electronic device and method for analogue to digital conversion according to Delta-Sigma modulation using double sampling 审中-公开
标题翻译：一种电子装置和方法，用于模拟 - 数字转换按照所述Δ-Σ调制使用双采样
公开(公告)号：EP2658131A1
公开(公告)日：2013-10-30
申请号：EP12002892.3
申请日：2012-04-24
申请人： Texas Instruments Deutschland , Texas Instruments Incorporated
发明人： Schmid, Konstantin , Reinhold, Michael , Ohnhaeuser, Frank
IPC分类号： H03M3/02
CPC分类号： H03M3/338 , H03M3/34 , H03M3/43 , H03M3/47
摘要： The invention relates to an electronic device and a method for analogue-to-digital conversion according to Delta-Sigma modulation. The modulator comprises at least a first switched capacitor integration stage (INT1), a second switched capacitor integration stage and a single-bit comparator, wherein the first switched capacitor Integration stage (INT1) is implemented in a fully differential architecture and comprises: an operational amplifier (OP1), a plurality of sets of input sampling capacitors (CIN1-CIN4) for sampling an analogue input voltage (VIN) and a plurality of sets of reference feedback capacitors (CRF1-CRF8) for sampling a feedback reference voltage (VREF), and wherein the first integration stage (INT1) is further configured to sample the analog input voltage (VIN) on a first set of input capacitors (CIN1, CIN2; CIN3, CIN4) out of the plurality of sets of input capacitors (CIN1-CIN4) during a first portion of a clock cycle and on a second set (CIN3, CIN4; CIN1, CIN2) out of the plurality of sets of input capacitors (CIN1-CIN4) during a second portion of the clock cycle and to sample the feedback reference voltage (VREF) on a first set of reference feedback capacitors (CRF1, CRF2; CRF3, CRF4; CRF5, CRF6; CRF7, CRF8) out of the plurality of sets of reference feedback capacitors (CRF1-CRF8) during the first portion of the clock cycle and on a second set of reference feedback capacitors (CRF1, CRF2; CRF3, CRF4; CRF5, CRF6; CRF7, CRF8) out of the plurality of sets of reference feedback capacitors (CRF1-CRF8) during the second portion of the clock cycle and wherein the first set of reference feedback capacitors and the second set of reference feedback capacitors are randomly selected out of the plurality of sets of reference feedback capacitors (CRF1-CRF8) from clock cycle to clock cycle.
摘要翻译：本发明涉及在电子装置和用于模拟 - 数字转换gemäß到delta-sigma调制的方法。所述调制器包括至少一个第一开关电容积分级（INT1），第二开关电容积分级和一个单个位比较器，worin第一开关电容积分级（INT1）在全差分结构，并包括被实现：运算放大器（OP1），用于模拟输入电压（VIN）和套参考反馈电容器（CRF1 CRF8）用于采样反馈参考电压的多个采样组输入取样电容器（CIN1 CIN4）的多个（VREF）和worin第一积分级（INT1）被进一步配置为在第一组输入电容器的采样模拟输入电压（VIN）（CIN1，CIN2，CIN3，CIN4）出的组输入电容器的多个（CIN1- CIN4）期间的时钟周期的第一部分和在第二组（CIN3，CIN4; CIN1，CIN2）出的组输入电容（CIN1 CIN4）的多个期间，在时钟周期的第二部分，并以采样反馈参考， NCE电压（VREF）上的第一组参考反馈电容器（CRF1，CRF2; CRF3，CRF4; CRF5，CRF6; CRF7，CRF8）选自组参考反馈电容器（CRF1 CRF8）的时钟周期的第一部分期间与在第二组参考反馈电容器（CRF1，CRF2多个; CRF3，CRF4; CRF5，CRF6; CRF7 ，在时钟周期的第二部分和worin所述第一组参考反馈电容器和第二组参考反馈电容器期间CRF8）选自组参考反馈电容器（CRF1 CRF8）多个随机选择从所述多个套从时钟周期参考反馈电容器（CRF1 CRF8）时钟周期。

7. 发明授权

EP1411639B1 A Sigma-Delta (SD) Analog-To-Digital Converter (ADC) structure incorporating a direct sampling mixer 有权
标题翻译： Σ-Δ模拟到数字转换器装置与一直接采样混频
公开(公告)号：EP1411639B1
公开(公告)日：2008-03-26
申请号：EP03103860.7
申请日：2003-10-17
申请人： Texas Instruments Incorporated
发明人： Staszewski, Robert B. , Chen, Feng , Muhammad, Khurram , Leipold, Dirk
IPC分类号： H03M3/02
CPC分类号： H03M3/47 , H03M3/496 , H04B1/1036

8. 发明授权

EP1421697B1 METHOD AND APPARATUS FOR CONTROLLING STAGES OF A MULTI-STAGE CIRCUIT 有权
标题翻译：为了控制方法和设备级的多级电路
公开(公告)号：EP1421697B1
公开(公告)日：2007-10-17
申请号：EP01993064.3
申请日：2001-10-31
申请人： QUALCOMM INCORPORATED
发明人： BAZARJANI, Seyfollah , WANG, Sean , PELUSO, Vincenzo
IPC分类号： H03M3/02
CPC分类号： H03M3/32 , H03M3/394 , H03M3/406 , H03M3/418 , H03M3/47
摘要： A control mechanism that can be used to control a SIGMA DELTA to provide the required level of performance while reducing power consumption. The SIGMA DELTA ADC is designe dwith multiple stage (i.e., loops or sections), and provides improved performance (e.g., higher dynamic range) as more stages are enabled. The control mechanism selectively enables a sufficient number of stages to provide the required performance and disables remaining stages to conserve power. The control mechanism achieves this by measuring one or more characteristics (e.g., signal level) of the ADC input signal through a SIGMA DELTA ADC that is similar to the SIGMA DELTA ADC on the signal path, comparing the measured characteristic(s) to particular threshold level(s), and controlling the stages such that the desired objectives are achieved. In one implementation, the control circuit includes one or more detector stages, a conditioning circuit, and a signal processor. The detector stage(s) receive the input signal and provide a detected signal. The conditioning circuit receives the detected signal and provides conditined samples. The signal processor receives the conditioned samples and provides a control signal that selectively disables zero or more SIGMA DELTA stages in the SIGMA DELTA ADC.

9. 发明授权

EP1401105B1 Voltage offset compensation method for time-interleaved multi-path analog-to-digital sigma-delta converters and respective circuit 有权
标题翻译：对于并行的流水线模数转换器和电路，用于偏移电压补偿方法
公开(公告)号：EP1401105B1
公开(公告)日：2006-06-14
申请号：EP02425563.0
申请日：2002-09-17
申请人： Siemens Mobile Communications S.p.A.
发明人： Gatti, Umberto , Malcovati, Piero , Ferragina, Vincenzo , Fornasari, Andrea
IPC分类号： H03M1/10
CPC分类号： H03M3/384 , H03M3/47

10. 发明公开

EP1411639A2 A Sigma-Delta (SD) Analog-To-Digital Converter (ADC) structure incorporating a direct sampling mixer 有权
标题翻译： Sigma-Delta Analog-Digital-Wandleranordnung mit einem direkt abtastenden Mischer
公开(公告)号：EP1411639A2
公开(公告)日：2004-04-21
申请号：EP03103860.7
申请日：2003-10-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Staszewski, Robert B. , Chen, Feng , Muhammad, Khurram , Leipold, Dirk
IPC分类号： H03M3/02
CPC分类号： H03M3/47 , H03M3/496 , H04B1/1036
摘要： A sigma-delta analog-to-digital converter offers advantages such as noise shaping and high frequency operation. However, a sampling circuit needed to provide a highly oversampled discrete-time sample stream with low noise characteristics is difficult to design and implement. The present invention provides a sigma-delta mixer 300 with such a sampling circuit 310. The present invention discloses a sampling circuit using switched capacitors 307, 308, and 309 with low noise characteristics and at the same time is capable of providing a highly oversampled discrete-time sample stream.
摘要翻译： Σ-Δ模数转换器提供了诸如噪声整形和高频操作等优点。然而，需要提供具有低噪声特性的高度过采样的离散时间采样流所需的采样电路难以设计和实现。本发明提供了具有这种采样电路310的Σ-Δ混合器300.本发明公开了一种使用具有低噪声特性的开关电容器307,308和309的采样电路，并且同时能够提供高度过采样的离散时间采样流。

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