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1. 发明授权

EP3041181B1 DRIVER CIRCUIT FOR SIGNAL TRANSMISSION AND CONTROL METHOD OF DRIVER CIRCUIT 有权
标题翻译：驱动电路信号传输驱动电路及控制方法
公开(公告)号：EP3041181B1
公开(公告)日：2017-09-13
申请号：EP15186369.3
申请日：2015-09-23
申请人： MediaTek Inc.
发明人： LUO, Yan-Bin , WU, Chien-Hua , LIN, Chung-Shi , LIN, Chih-Hsien
IPC分类号： H03K17/10 , H04L25/02 , H04L25/49
CPC分类号： H03K17/10 , H04L25/0272 , H04L25/0282 , H04L25/4906

2. 发明公开

EP3136436A1 MULTI-CHIP STRUCTURE HAVING FLEXIBLE INPUT/OUTPUT CHIPS 审中-公开
标题翻译：美国芝加哥麻省理工学院ELEXANGS- / AUSGANGS-CHIPS
公开(公告)号：EP3136436A1
公开(公告)日：2017-03-01
申请号：EP16161680.0
申请日：2016-03-22
申请人： MediaTek, Inc
发明人： LUO, Yan-Bin , YIN, Hao-Hui , YU, Chih-Ching , SU, Yao-Chun
IPC分类号： H01L25/065 , H01L25/18 , H03M9/00 , H04L12/24 , H04L12/935
CPC分类号： H04L49/40 , H01L25/0655 , H01L25/18 , H01L2224/16227 , H01L2224/16235 , H01L2924/15192 , H01L2924/15311 , H03M9/00 , H04L49/30
摘要： A multi-chip structure comprises a switch system on chip (switch SOC) (110), a plurality of serializer/deserializer (SerDes) chips (120_1-120_4) positioned around the switch SOC (100), and a plurality of inter-chip interfaces (130_1-130_4) for connecting the switch SOC (110) to the plurality of SerDes chips (120_1-1 20_4), respectively.
摘要翻译：多芯片结构包括片上开关系统（开关SOC）（110），位于开关SOC（100）周围的多个串行器/解串器（SerDes）芯片（120_1-120_4），以及多个芯片间用于将开关SOC（110）分别连接到多个SerDes芯片（120_1-120_4）的接口（130_1-130_4）。

3. 发明公开

EP2991297A1 METHOD FOR PERFORMING LOOP UNROLLED DECISION FEEDBACK EQUALIZATION IN AN ELECTRONIC DEVICE WITH AID OF VOLTAGE FEEDFORWARD, AND ASSOCIATED APPARATUS 有权
标题翻译：方法用于进行“循环展开”判决反馈均衡器的电子设备中使用电源前馈补偿及相关设备
公开(公告)号：EP2991297A1
公开(公告)日：2016-03-02
申请号：EP15173083.5
申请日：2015-06-22
申请人： MediaTek, Inc
发明人： CHOU, Tsung-Hsin , LIN, Chih-Hsien , WANG, Huai-Te , CHEN, Bo-Jiun , LUO, Yan-Bin
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L25/03885 , H04L2025/03484 , H04L2025/0349 , H04L2025/03777 , H04L2025/03808
摘要： A method for performing loop unrolled decision feedback equalization (DFE) and an associated apparatus (100) are provided. The method includes: receiving a tap control signal and an offset control signal from a digital domain of a DFE receiver in an electronic device (100), and generating DFE information respectively corresponding to the tap control signal and the offset control signal in an analog domain of the DFE receiver; broadcasting the DFE information respectively corresponding to the tap control signal and the offset control signal toward comparators (118-1, 118-2, 430-1, 430-2, 430-3, 430-4, 430-5, 430-6) in the DFE receiver; utilizing the comparators (118-1, 118-2, 430-1, 430-2, 430-3, 430-4, 430-5, 430-6) to perform comparison operations according to the DFE information respectively corresponding to the tap control signal and the offset control signal to generate comparison results; and selectively adjusting the tap control signal and the offset control signal according to the comparison results, to optimize the DFE information respectively corresponding to the tap control signal and the offset control signal, respectively.
摘要翻译：本发明提供一种用于执行循环展开判决反馈均衡（DFE）和相关联的设备（100）的方法。该方法包括：接收一个抽头控制信号，并且在给电子设备（100）从一个DFE接收机的数字域偏移控制信号，以及生成DFE信息分别对应于所述抽头控制信号和在模拟域中的偏移控制信号在DFE接收机的; 广播所述DFE信息分别对应于所述抽头控制信号和向比较器（118-1，118-2，430-1，430-2，430-3，430-4，430-5的偏移控制信号，430-6 ）在DFE接收机; 利用比较器（118-1,118-2，430-1，430-2，430-3，430-4，430-5，430-6），以执行比较操作分别。据DFE信息到抽头CORRESPONDING 控制信号和所述偏移控制信号，以产生比较结果; 和选择性地调节所述抽头控制信号和所述偏移控制信号gemäß比较结果，分别以优化DFE信息分别对应于所述抽头控制信号和所述偏移控制信号，。

4. 发明公开

EP3171376A1 INDUCTOR AND INDUCTOR MODULE 审中-公开
标题翻译：电感和电感模块
公开(公告)号：EP3171376A1
公开(公告)日：2017-05-24
申请号：EP16172858.9
申请日：2016-06-03
申请人： MediaTek Inc.
发明人： CHEN, Huan-Sheng , LU, Yen-Ju , LIN, Chung-Shi , WU, Chien-Hua , LUO, Yan-Bin
IPC分类号： H01F38/14 , H01F27/28
CPC分类号： H01F27/28 , H01F27/2804 , H01F27/29 , H01F38/14
摘要： An inductor module characterized by: a first inductor (L_1), comprising a first inductor area (IA_1); and a second inductor (L_2), comprising a second inductor area (IA_2). A first overlapped area of the first inductor area and a second overlapped area of the second inductor area are overlapped. The second overlapped area comprises at least one first magnetic direction area (MA_1) and at least one second magnetic direction area (MA_2). A ratio between a size of the first magnetic direction area (MA_1) and a size of the second magnetic direction area (MA_2) is a predetermined ratio such that a coupling effect between the first inductor (L_1) and the second inductor (L_2) is lower or equals to a predetermined value.
摘要翻译：一种电感器模块，其特征在于：第一电感器（L_1），其包括第一电感器区域（IA_1）; 和第二电感器（L_2），其包括第二电感器区域（IA_2）。第一电感器区域的第一重叠区域与第二电感器区域的第二重叠区域重叠。第二重叠区域包括至少一个第一磁性方向区域（MA_1）和至少一个第二磁性方向区域（MA_2）。第一磁方向区域（MA_1）的大小与第二磁方向区域（MA_2）的大小之间的比率是预定比率，使得第一电感器（L_1）和第二电感器（L_2）之间的耦合效应是降低或等于预定值。

5. 发明公开

EP2991260A1 METHOD FOR PERFORMING DATA SAMPLING CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS 有权
标题翻译：方法具体日期采样控制在一种电子装置和相关设备
公开(公告)号：EP2991260A1
公开(公告)日：2016-03-02
申请号：EP15173852.3
申请日：2015-06-25
申请人： MediaTek, Inc
发明人： WANG, Huai-Te , CHOU, Tsung-Hsin , LIN, Chih-Hsien , CHEN, Bo-Jiun , LUO, Yan-Bin
IPC分类号： H04L7/033 , H04L25/03
CPC分类号： H04L25/03057 , H03L7/087 , H03L7/091 , H03L7/095 , H03L7/099 , H04L7/0025 , H04L7/0331 , H04L25/063
摘要： A method for performing data sampling control in an electronic device (100, 300) and an associated apparatus (100, 300) are provided, where the method includes the steps of: detecting whether a data pattern of a received signal of a decision feedback equalizer (DFE) receiver in the electronic device matches a predetermined data pattern, to selectively trigger a data sampling time shift configuration of the DFE receiver; and when the data sampling time shift configuration is triggered, utilizing a phase shift clock (CK EDGE , CK DELAY ), rather than a normal clock (CK 180 ) corresponding to a normal configuration of the DFE receiver, as an edge sampler clock (CK EDGE ) of an edge sampler (114) in the DFE receiver, to lock onto edge timing of the received signal, and controlling the phase shift clock and the normal clock to have different phases, respectively, to shift data sampling time of the DFE receiver, for performing data sampling in the DFE receiver.
摘要翻译：提供了一种用于在电子设备中执行数据采样控制（100，300）和相关联的设备（100，300）的方法，其中该方法包括以下步骤：检测是否一个判决反馈均衡器的接收信号的数据图案（DFE）接收器在电子装置中的预定数据模式相匹配，以选择性地触发所述DFE接收机的数据采样时移的配置; 并且当数据抽样时移的配置被触发时，利用一个相位偏移的时钟（CK EDGE，克·德利），而不是一个正常的时钟（CK 180）对应于所述DFE接收机的正常结构中，作为上边缘采样时钟（CK 在DFE接收机的边缘采样器（114）的EDGE），锁定到所接收的信号的边缘定时，并且控制所述相移时钟与正常时钟具有不同的相位，分别将数据移出所述DFE接收机的采样时间，在DFE接收机进行数据采样。

6. 发明授权

EP2991260B1 METHOD FOR PERFORMING DATA SAMPLING CONTROL IN AN ELECTRONIC DEVICE, AND ASSOCIATED APPARATUS 有权
公开(公告)号：EP2991260B1
公开(公告)日：2019-04-03
申请号：EP15173852.3
申请日：2015-06-25
申请人： MediaTek Inc.
发明人： WANG, Huai-Te , CHOU, Tsung-Hsin , LIN, Chih-Hsien , CHEN, Bo-Jiun , LUO, Yan-Bin
IPC分类号： H04L7/033 , H04L25/03

7. 发明公开

EP3208813A1 COMPOSITE INDUCTOR STRUCTURE 审中-公开
标题翻译：复合电感结构
公开(公告)号：EP3208813A1
公开(公告)日：2017-08-23
申请号：EP16181032.0
申请日：2016-07-25
申请人： MediaTek Inc.
发明人： CHEN, Huan-Sheng , LUO, Yan-Bin
IPC分类号： H01F17/00 , H01F27/34
CPC分类号： H01F27/2804 , H01F17/0006 , H01F27/346 , H01F2017/0073
摘要： A composite inductor structure (300, 400, 500) is provided, which comprises: a first spiral inductor (310, 410, 510) and a second spiral inductor (320, 420, 520). The first spiral inductor (310, 410, 510) has a plurality of loops and generates a first electromagnetic field, wherein an outermost loop of the first spiral inductor (310, 410, 510) has a first end point (312, 412, 512), and an innermost loop of the first spiral inductor (310, 410, 510) has a second end point (314, 414, 514). The second spiral inductor (320, 420, 520) is arranged to be adjacent to the first spiral inductor, and has a plurality of loops and generates a second electromagnetic field, wherein an outermost loop of the second spiral inductor (320, 420, 520) has a third end point (322, 422, 522), and an innermost loop of the second spiral inductor (320, 420, 520) has a fourth end point (324, 424, 524), and the second spiral inductor (320, 420, 520) is rotated by a specific degree with respect to an orientation of the first spiral inductor (310, 410, 510), and the first electromagnetic field and the second electromagnetic field are oppositely directed.
摘要翻译：提供复合电感器结构（300,400,500），其包括：第一螺旋电感器（310,410,510）和第二螺旋电感器（320,420,520）。第一螺旋电感器（310,410,510）具有多个环路并且产生第一电磁场，其中第一螺旋电感器（310,410,510）的最外环路具有第一端点（312,412,512）），并且第一螺旋电感器（310,410,510）的最内圈具有第二端点（314,414,514）。第二螺旋电感器（320,420,520）被布置成与第一螺旋电感器相邻并且具有多个环并且产生第二电磁场，其中第二螺旋电感器（320,420,520）的最外环）具有第三端点（322,422,522），并且第二螺旋电感器（320,420,520）的最内环路具有第四端点（324,424,524），并且第二螺旋电感器，420,520）相对于第一螺旋电感器（310,410,510）的取向旋转特定的程度，并且第一电磁场和第二电磁场相反指向。

8. 发明公开

EP3174209A1 DRIVER CIRCUIT FOR SIGNAL TRANSMISSION 审中-公开
标题翻译：信号传输驱动电路
公开(公告)号：EP3174209A1
公开(公告)日：2017-05-31
申请号：EP16169102.7
申请日：2016-05-11
申请人： MediaTek Inc.
发明人： WU, Chien-Hua , LUO, Yan-Bin
IPC分类号： H03K19/0175
CPC分类号： H03K19/017527
摘要： A driver circuit (100) for receiving a data input and generating an output signal to a termination element according to at least the first data input is provided. The driver circuit (100) includes a first output terminal, a current mode drive unit (110) and a voltage mode drive unit (120). The current mode drive unit (110) is arranged for selectively outputting a first reference current from the first output terminal to the termination element according to the first data input, and selectively receiving the first reference current through the first output terminal according to the first data input. The voltage mode drive unit (120) is arranged for coupling one of a first reference voltage and a second reference voltage different from the second reference voltage to the first output terminal according to the first data input.
摘要翻译：提供了用于接收数据输入并根据至少第一数据输入产生到终端元件的输出信号的驱动器电路（100）。驱动器电路（100）包括第一输出端子，电流模式驱动单元（110）和电压模式驱动单元（120）。电流模式驱动单元（110）用以根据第一数据输入选择性地输出第一参考电流至第一输出端，并根据第一数据选择性地接收第一参考电流通过第一输出端输入。电压模式驱动单元（120）用于根据第一数据输入将第一参考电压和不同于第二参考电压的第二参考电压中的一个耦合到第一输出端。

9. 发明公开

EP3043476A1 DRIVER CIRCUIT WITH FEED-FORWARD EQUALIZER 有权
标题翻译： TREIBERSCHALTUNG MIT VORSCHUB-ENTZERRER
公开(公告)号：EP3043476A1
公开(公告)日：2016-07-13
申请号：EP15186808.0
申请日：2015-09-25
申请人： MediaTek, Inc
发明人： LUO, Yan-Bin , WU, Chien-Hua , LIN, Chung-Shi , LIN, Chih-Hsien
IPC分类号： H03K19/0175 , H03K19/0185
CPC分类号： H03K3/012 , H03K19/017509 , H03K19/018528 , H03K19/018585 , H04L25/03076
摘要： A driver circuit (100) for receiving input data and generating an output signal to a termination element (R T ) is provided, wherein the input data has a first bit and second bit, and the driver circuit (100) includes: a pair of differential output terminals (T1, T2) for outputting the output signal, wherein the pair of differential output terminals (T1, T2) has a first output terminal (T1) and a second output terminal (T2); at least one current mode drive unit (110), coupled to the pair of differential output terminals (T1, T2), for outputting a current from one of the first output terminal (T1) and the second output terminal (T2), and receiving the current from the other of the first output terminal (T1) and the second output terminal (T2) according to the first bit; and at least one voltage mode drive unit (120), coupled to the pair of differential output terminals (T1, T2), for providing voltages to the first output terminal (T1) and the second output terminal (T2) according to the second bit.
摘要翻译：提供了一种用于接收输入数据并向终端元件（RT）产生输出信号的驱动器电路（100），其中输入数据具有第一位和第二位，并且驱动器电路（100）包括：一对差分输出端子（T1，T2），其中所述一对差分输出端子（T1，T2）具有第一输出端子（T1）和第二输出端子（T2）; 耦合到所述一对差分输出端子（T1，T2）的至少一个电流模式驱动单元（110），用于从所述第一输出端子（T1）和所述第二输出端子（T2）之一输出电流，以及接收根据第一位从第一输出端子（T1）和第二输出端子（T2）中的另一个的电流; 以及耦合到所述一对差分输出端子（T1，T2）的至少一个电压模式驱动单元（120），用于根据所述第二位置向所述第一输出端子（T1）和所述第二输出端子（T2）提供电压。

10. 发明公开

EP3896576A1 MULTI-PACKAGE SYSTEM USING CONFIGURABLE INPUT/OUTPUT INTERFACE CIRCUITS FOR SINGLE-ENDED INTRA-PACKAGE COMMUNICATION AND DIFFERENTIAL INTER-PACKAGE COMMUNICATION 审中-实审
公开(公告)号：EP3896576A1
公开(公告)日：2021-10-20
申请号：EP21156383.8
申请日：2021-02-10
申请人： MediaTek Inc.
发明人： YEH, Chun-Yuan , LUO, Yan-Bin , HSU, Tse-Hsiang
IPC分类号： G06F13/40
摘要： A multi-package system includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first die and a second die. The second semiconductor package includes a third die. A first processing circuit of the first die communicates with a second processing circuit of the second die through a first configurable input/output (IO) interface circuit of the first die and a third configurable IO interface circuit of the second die that are configured to perform single-ended intra-package communication. The first processing circuit of the first die communicates with a third processing circuit of the third die through a second configurable IO interface circuit of the first die and a fourth configurable IO interface circuit of the third die that are configured to perform differential inter-package communication. The first configurable IO interface circuit and the second configurable IO interface circuit have a same circuit design.

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