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1. 发明公开

EP4373053A1 SCALABLE MULTI-PLANE FABRIC-LESS CONNECTIVITY FOR PACKET FORWARDING ENGINE 审中-公开
公开(公告)号：EP4373053A1
公开(公告)日：2024-05-22
申请号：EP23150995.1
申请日：2023-01-10
申请人： Juniper Networks, Inc.
发明人： THOMAS, Philip A. , POON, Wing , KHICHA, Ashish , AGASHE, Harshad B. , BASU, Arghajit , JAIN, Naveen Kumar
IPC分类号： H04L49/15 , H04L49/25 , H04L49/00
CPC分类号： H04L49/15 , H04L49/25 , H04L49/30
摘要： A network device includes one or more dies, wherein each die, of the one or more dies includes one or more packet forwarding components and a switch fabric component. The switch fabric component of a particular die, of the one or more dies, may be connected to the one or more forwarding components of the particular die, and may be configured to provide a switching plane for the one or more packet forwarding components of the particular die. A first die, of the one or more dies, may be connected to the one or more packet forwarding components of a second die of the one or more dies, and may be configured to provide a switching plane for the one or more packet forwarding components of the second die.

2. 发明授权

EP4030646B1 PACKET FORWARDING METHOD, DEVICE AND SYSTEM 有权转让
公开(公告)号：EP4030646B1
公开(公告)日：2024-04-24
申请号：EP20871409.7
申请日：2020-09-17
IPC分类号： H04J3/06 , H04L47/283 , H04L47/56 , H04L49/00 , H04L49/25
CPC分类号： H04L47/283 , H04L47/56 , H04L49/25 , H04L49/30 , H04J3/0658

3. 发明授权

EP3223479B1 CHIP AND TRANSMISSION SCHEDULING METHOD 有权
公开(公告)号：EP3223479B1
公开(公告)日：2018-11-14
申请号：EP17161529.7
申请日：2017-03-17
申请人： Huawei Technologies Co., Ltd.
发明人： XIN, Hengchao , LIN, Han , XIA, Jing
IPC分类号： H04L12/933 , H04L12/935 , G06F13/38
CPC分类号： H04L49/30 , H04L43/08 , H04L49/109
摘要： Embodiments of the present invention relate to the field of chips, and provide a chip and a transmission scheduling method. The chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: monitor a queue depth of a processing queue of outputting data from the first die to the second die, and when the queue depth reaches a first preset threshold, by means of handshaking with the second processing unit, switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input. A prior-art problem that a resource waste may be caused because interconnection resources of a physical layer interface between dies cannot be fully utilized is resolved.

4. 发明公开

EP3238390A4 COMBINED GUARANTEED THROUGHPUT AND BEST EFFORT NETWORK-ON-CHIP 有权
公开(公告)号：EP3238390A4
公开(公告)日：2018-07-18
申请号：EP15873990
申请日：2015-11-24
申请人： INTEL CORP
发明人： CHEN GREGORY K , ANDERS MARK A , KAUL HIMANSHU , KRISHNAMURTHY RAM K , STILLMAKER AARON T
IPC分类号： H04L12/771 , G06F13/14 , G06F15/78 , H04L12/64 , H04L12/863 , H04L12/911 , H04L12/931 , H04L12/935
CPC分类号： H04L47/625 , G06F15/7825 , H04L12/6402 , H04L47/72 , H04L49/30
摘要： A first packet-switched reservation request is received. Data associated with the first packet-switched reservation request is communicated through a first circuit-switched channel according to a best effort communication scheme. A second packet-switched reservation request is received. Data associated with the second packet-switched reservation request is communicated through a second circuit-switched channel according to a guaranteed throughput communication scheme.

5. 发明授权

EP2856719B1 TECHNIQUE DE COMMUNICATION DANS UN RÉSEAU DE COMMUNICATION CENTRÉ SUR LES INFORMATIONS 有权
标题翻译：通信技术在信息集中通信网络中的应用
公开(公告)号：EP2856719B1
公开(公告)日：2018-04-25
申请号：EP13729992.1
申请日：2013-05-17
申请人： Orange
发明人： MUSCARIELLO, Luca , CAROFIGLIO, Giovanna
IPC分类号： H04L12/801 , H04L12/823 , H04L12/811 , H04L29/08
CPC分类号： H04L45/44 , H04L47/19 , H04L47/32 , H04L49/30 , H04L67/327

6. 发明授权

EP2337305B1 Header processing engine 有权转让
标题翻译：头部处理引擎
公开(公告)号：EP2337305B1
公开(公告)日：2018-01-24
申请号：EP10195863.5
申请日：2010-12-20
申请人： Solarflare Communications Inc
发明人： Pope, Steve , Riddoch, David , Kitariev, Dimitri , Roberts, Derek
IPC分类号： H04L29/06 , H04L12/935 , H04L12/741
CPC分类号： H04L45/74 , H04L49/30 , H04L69/22
摘要： A header processing engine for a network interface device having a buffer for holding one or more data packets each having one or more headers, the header processing engine comprising: a command memory; a header recognizer configured to parse the headers of a data packet stored at the buffer so as to identify the type and position of each header in the data packet; a constructor unit having read access to the headers of the data packet; and a processor including an execution pipeline; the header recognizer being further configured to, for each header: (a) select in dependence on the type of the header one or more commands stored at the command memory; and (b) form one or more messages for the constructor unit identifying the selected commands and the position of the header in the data packet; the commands selected for the headers of the data packet being collectively such as to, if executed by the constructor unit, cause the constructor unit to generate a data structure which is such as to be operable to cause the processor to effect processing of the headers of the data packet without accessing the data packet at the buffer; and the constructor unit being configured to receive the messages and execute the commands identified therein.

7. 发明公开

EP3175591A4 SYSTEM AND METHOD FOR CONTROLLER REDUNDANCY AND CONTROLLER NETWORK REDUNDANCY WITH ETHERNET/IP I/O 有权
公开(公告)号：EP3175591A4
公开(公告)日：2017-12-27
申请号：EP15827818
申请日：2015-07-22
申请人： HONEYWELL INT INC
发明人： BALE SUNIL , ATUKURI SRINIVAS , FELIX JOSEPH
IPC分类号： H04L12/939 , H04L12/24 , H04L12/40 , H04L12/937
CPC分类号： H04L41/0677 , H04L12/40176 , H04L41/0663 , H04L49/30 , H04L49/555
摘要： An apparatus includes a first controller having at least one interface and at least one processing device. The at least one interface is configured to communicate with a second controller and with a controlled network having multiple EtherNet/IP-compatible input/output (I/O) modules and multiple EtherNet/IP-compatible controlled devices. The at least one processing device is configured to detect a fault associated with the second controller while the second controller is in communication with at least one of the I/O modules and at least one of the controlled devices. The at least one processing device is also configured, upon detection of the fault associated with the second controller, to resume the communication with the at least one I/O module and the at least one controlled device without the at least one I/O module updating the at least one controlled device to a failsafe condition.

8. 发明授权

EP2899926B1 METHOD FOR IMPLEMENTING PACKET SEARCHING BY USING TWO SLIDING WINDOWS 有权
标题翻译：通过使用两个滑动窗口来实现分组搜索的方法
公开(公告)号：EP2899926B1
公开(公告)日：2017-11-29
申请号：EP14754402.7
申请日：2014-01-23
申请人： Inspur Electronic Information Industry Co., Ltd.
发明人： WANG, Endong , HU, Leijun , LI, Rengang
IPC分类号： H04L12/70 , H04L12/935 , H04L12/931 , H04L12/46 , H04L12/26
CPC分类号： H04L43/50 , H04L12/4625 , H04L49/30 , H04L49/40
摘要： A method of implementing packet search by double sliding windows is provided. The method adopts a three-level barrel shift register to store input packet data, and a position of a sliding window 1 is determined at 32 positions by primary testing of a link, so as to ensure that the packet data is located at the center of the sliding window 1, thereby ensuring that the position of the sliding window 1 meets a transmission characteristic of a specific link to the maximum extent. After the position of the sliding window 1 is determined, 32-bit packet data can be effectively searched in the sliding window 1 by dynamically adjusting a sliding window 2, and 32-bit transmission offset is allowed for the packet data. The method of implementing packet search by double sliding windows meets a transmission characteristic of a specific link to the maximum extent.

9. 发明公开

EP2720390A3 Method for implementing a multi-chip module with a high-rate interface 有权转让
标题翻译：用于实现具有高速率接口的多芯片模块的方法
公开(公告)号：EP2720390A3
公开(公告)日：2017-11-29
申请号：EP13004860.6
申请日：2013-10-09
申请人： Avago Technologies General IP (Singapore) Pte. Ltd.
发明人： Woodruff, William
IPC分类号： H04J3/06 , H04J3/04 , H04L29/06 , H04L12/741 , H04L12/931 , H04L12/935
CPC分类号： H04L49/30 , H04J3/047 , H04J3/0697 , H04L45/745 , H04L49/40
摘要： A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.
摘要翻译：多芯片模块（MCM）可以包括衬底，以及安装在衬底上的第一和第二物理层（PHY）芯片。在一些实现中，第一PHY芯片包括多路复用器和PHY电路。复用器被配置为从媒体访问控制（MAC）设备接收复用数据流，将复用数据流解复用为第一和第二数据流，将第一数据流输出到PHY电路，并输出第二数据流到第二PHY芯片。在一些实现中，第一PHY包括路由器和PHY电路。路由器被配置为从MAC设备接收多个数据分组，以将具有第一地址的一个或多个数据分组路由到PHY电路，并且将具有第二地址的一个或多个数据分组路由到第二PHY芯片。

10. 发明公开

EP3223479A1 CHIP AND TRANSMISSION SCHEDULING METHOD 有权
标题翻译：芯片和传输调度方法
公开(公告)号：EP3223479A1
公开(公告)日：2017-09-27
申请号：EP17161529.7
申请日：2017-03-17
申请人： Huawei Technologies Co., Ltd.
发明人： XIN, Hengchao , LIN, Han , XIA, Jing
IPC分类号： H04L12/933 , G06F13/38
CPC分类号： H04L49/30 , H04L43/08 , H04L49/109
摘要： Embodiments of the present invention relate to the field of chips, and provide a chip and a transmission scheduling method. The chip is formed by packaging at least two dies, and the at least two dies form at least one die group. The die group includes a first die and a second die. A first processing unit and n groups of ports are disposed on the first die, and a second processing unit and m groups of ports are disposed on the second die. The first processing unit is configured to: monitor a queue depth of a processing queue of outputting data from the first die to the second die, and when the queue depth reaches a first preset threshold, by means of handshaking with the second processing unit, switch at least one group of first type ports in the n groups of ports from input to output and switch a second type port that is in the m groups of ports and that is coupled to each group of the first type ports from output to input. A prior-art problem that a resource waste may be caused because interconnection resources of a physical layer interface between dies cannot be fully utilized is resolved.
摘要翻译：本发明实施例涉及芯片领域，提供一种芯片和传输调度方法。芯片通过封装至少两个管芯而形成，并且至少两个管芯形成至少一个管芯组。模组包括第一模具和第二模具。第一处理单元和n组端口设置在第一管芯上，第二处理单元和m组端口设置在第二管芯上。所述第一处理单元用于监测从所述第一裸片向所述第二裸片输出数据的处理队列的队列深度，当所述队列深度达到第一预设阈值时，通过与所述第二处理单元的握手，切换所述n组端口中的至少一组第一类型端口从输入到输出并且切换第二类型端口，所述第二类型端口在所述m组端口中并且从输出到输入耦合到每组第一类型端口。解决了由于裸片之间的物理层接口的互连资源不能被充分利用而可能导致资源浪费的现有技术问题。

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