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1. 发明公开

EP0325105A1 Multiport memory 失效
标题翻译：多端口，斯派克。
公开(公告)号：EP0325105A1
公开(公告)日：1989-07-26
申请号：EP89100100.0
申请日：1989-01-04
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Ohshima, Shigeo , Toda, Haruki , Ikawa, Tatsuo
IPC分类号： G11C7/00 , G11C8/00 , G06F12/00
CPC分类号： G11C7/1075
摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL , a word line WL, a data transfer gate φDT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate φDT.
摘要翻译：本发明提供一种多端口存储器，其包括具有位线BL和BL的存储部分A，字线WL，数据传送门极DT和动态存储单元Cs，以及具有串行访问功能的串行端口B 存储部分的方向，其中存储器包括一个电路，用于禁止字线信号WL用于在传输周期中在存储单元保存的数据被传输的传输周期中提高行地址选通信号RAS的条件下选择一个字线到串行端口，并且数据传输到串行端口的数据传输门phi DT完成。

2. 发明授权

EP0328110B1 Operation mode setting circuit for DRAM 失效
标题翻译：电路用于设置DRAM内存运行模式。
公开(公告)号：EP0328110B1
公开(公告)日：1993-12-01
申请号：EP89102251.9
申请日：1989-02-09
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/406
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/4076

3. 发明公开

EP0328110A3 Operation mode setting circuit for DRAM 失效
标题翻译： DRAM的操作模式设置电路
公开(公告)号：EP0328110A3
公开(公告)日：1991-10-09
申请号：EP89102251.9
申请日：1989-02-09
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/406
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/4076
摘要： A signal ( WE ) externally supplied to determine operation mode is supplied to a first buffer circuit (13). A CAS signal is supplied to a second buffer circuit (14). The signals whose levels are converted by the first and second buffer circuits (13 and 14) are supplied to a mode selection circuit (15). The operation of the mode selection circuit (15) is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits (13 and 14). An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit (16). The address buffer circuit (16) selects one of the received address signals based on the RAS signal and the mode selection signal output from the mode selection circuit (15). A selected one of the address signals is supplied to a word line selection/driving circuit (17). When a mode other than the auto-refresh mode is specified, the mode setting signal ( WE ) is set up before the RAS signal is activated. The set-up allowance time (t S ) with respect to the activation timing of the RAS signal is set to be larger than the minimum value (t ASRmin ) of the set-up allowance time (t ASR ) of the external address signal. The mode setting signal ( WE ) is latched by the mode selection circuit (15) when the RAS signal is activated. The latched signal is used to select and control the operation mode.

4. 发明授权

EP0325105B1 Multiport memory 失效
标题翻译：多媒体内存
公开(公告)号：EP0325105B1
公开(公告)日：1992-08-05
申请号：EP89100100.0
申请日：1989-01-04
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Ohshima, Shigeo , Toda, Haruki , Ikawa, Tatsuo
IPC分类号： G11C7/00 , G11C8/00 , G06F12/00
CPC分类号： G11C7/1075

5. 发明公开

EP0328110A2 Operation mode setting circuit for DRAM 失效
标题翻译： Schaltung zur Einstellung des BetriebsmodusfürDRAM-Speicher。
公开(公告)号：EP0328110A2
公开(公告)日：1989-08-16
申请号：EP89102251.9
申请日：1989-02-09
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/406
CPC分类号： G11C11/406 , G11C7/1045 , G11C11/4076
摘要： A signal ( WE ) externally supplied to determine operation mode is supplied to a first buffer circuit (13). A CAS signal is supplied to a second buffer circuit (14). The signals whose levels are converted by the first and second buffer circuits (13 and 14) are supplied to a mode selection circuit (15). The operation of the mode selection circuit (15) is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits (13 and 14). An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit (16). The address buffer circuit (16) selects one of the received address signals based on the RAS signal and the mode selection signal output from the mode selection circuit (15). A selected one of the address signals is supplied to a word line selection/driving circuit (17). When a mode other than the auto-refresh mode is specified, the mode setting signal ( WE ) is set up before the RAS signal is activated. The set-up allowance time (t S ) with respect to the activation timing of the RAS signal is set to be larger than the minimum value (t ASRmin ) of the set-up allowance time (t ASR ) of the external address signal. The mode setting signal ( WE ) is latched by the mode selection circuit (15) when the RAS signal is activated. The latched signal is used to select and control the operation mode.
摘要翻译：外部提供的用于确定操作模式的信号（WE）被提供给第一缓冲电路（13）。 CAS信号被提供给第二缓冲电路（14）。其电平由第一和第二缓冲电路（13和14）转换的信号被提供给模式选择电路（15）。模式选择电路（15）的操作由RAS信号控制，并且基于第一和第二缓冲电路（13和14）的输出锁存和输出模式选择信号。外部提供的地址信号和在设备中形成的地址信号被提供给地址缓冲电路（16）。地址缓冲电路（16）基于RAS信号和从模式选择电路（15）输出的模式选择信号，选择接收的地址信号之一。所选择的一个地址信号被提供给字线选择/驱动电路（17）。当指定了自动刷新模式以外的模式时，模式设置信号（WE）在激活RAS信号之前建立。相对于RAS信号的激活定时的设定容许时间（tS）被设定为大于外部地址信号的设定容许时间（tASR）的最小值（tASRmin）。当RAS信号被激活时，模式设置信号（WE）被模式选择电路（15）锁存。锁存信号用于选择和控制操作模式。

6. 发明公开

EP0788107A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0788107A3
公开(公告)日：1999-06-02
申请号：EP97101347.9
申请日：1997-01-29
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kai, Yasuyuki , Nagaba, Katsushi , Ohshima, Shigeo
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C7/1078
摘要： A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array (11) having a plurality of dynamic memory cells, to which data can be written, data line pairs (DQ0, BDQ0 to DQN, BDQN) to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver (17) for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit (18) for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.
摘要翻译：本发明公开了一种半导体存储装置，该半导体存储装置能够缩短从写入模式向读取模式变更模式后的第一读取周期的数据读取时间，并且即使简单地构成写入数据也能够维持高速的周期时间，具有可向其写入数据的多个动态存储单元的存储单元阵列（11），从存储单元读取数据的数据线对（DQ0，BDQ0至DQN，BDQN）以及必须写入存储单元的数据当数据被写入存储器单元时，用于驱动数据线对的写入驱动器（17）根据外部提供的写入数据来驱动数据线对，以及均衡电路（18），用于无论何时将数据线对设置为中间电位数据线对由写入驱动器操作。

7. 发明公开

EP0420268A3 Function selector circuit 失效
标题翻译：功能选择器电路
公开(公告)号：EP0420268A3
公开(公告)日：1994-02-23
申请号：EP90118680.9
申请日：1990-09-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C7/1015
摘要： A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
摘要翻译：功能选择电路包括：第一信号发生电路（2），用于产生与多个输入信号状态的所有组合中的每一个相对应的多个第一信号; 和第二信号发生电路（5），用于选择多个第一信号的组合的多个逻辑和并产生对应于多个逻辑和中的每一个的第二信号，该第二信号选择性地激活由真值表指示的操作函数。

8. 发明公开

EP0359203A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0359203A2
公开(公告)日：1990-03-21
申请号：EP89116871.8
申请日：1989-09-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/409 , G11C11/408
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096
摘要： Memory cells (12,22...N2) disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by first gate means. One memory cell column in the n memory cell columns in a selected block is selected by second gate means. One memory cell (12,22...N2) in a selected memory cell column is selected by a row address. The data in a selected memory cell (12,22...N2) are stored in a register and output therefrom.
摘要翻译：设置在矩阵中的存储单元（12,22 ... N2）被分成多个块。每个块由n（n是大于2的正整数）的存储单元列构成。一个列由一个地址选择。所选块中n个存储单元列中的一个存储单元列由第一门装置选择。所选块中n个存储单元列中的一个存储单元列由第二门装置选择。所选存储单元列中的一个存储单元（12,22 ... N2）由行地址选择。所选存储单元（12,22 ... N2）中的数据被存储在寄存器中并由其输出。

9. 发明公开

EP0782143A2 A semiconductor memory circuit equipped with a column addressing circuit having a shift register 失效
标题翻译：米歇尔·埃勒（Spelltenadressierungsschaltung）ausgestattete Halbleiterspeicherschaltung mit Schieberegister
公开(公告)号：EP0782143A2
公开(公告)日：1997-07-02
申请号：EP96120772.7
申请日：1996-12-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Inuzuka, Kazuko , Ohshima, Shigeo , Nagaba, Katsushi
IPC分类号： G11C8/04
CPC分类号： G11C8/04
摘要： The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit (109) normally comprising a counter constitutes a shift register (SRG) in a column addressing circuit (109) at a preceding stage of a column address buffer (106) so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.
摘要翻译：本发明提供一种能够通过简化的高速寻址电路高速访问预定列部分的半导体存储器电路。 DRAM中的存储器电路使得通常包括计数器的列寻址电路（109）的一部分在列地址缓冲器（106）的前一级构成列寻址电路（109）中的移位寄存器（SRG）使得实现多个地址信号包装来访问预定的列部分。

10. 发明授权

EP0432509B1 Semiconductor memory device 失效
公开(公告)号：EP0432509B1
公开(公告)日：1997-06-11
申请号：EP90121917.0
申请日：1990-11-15
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kiryu, Masakazu , Ohshima, Shigeo
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/00 , G11C11/4096

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