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1. 发明公开

EP0420268A3 Function selector circuit 失效
标题翻译：功能选择器电路
公开(公告)号：EP0420268A3
公开(公告)日：1994-02-23
申请号：EP90118680.9
申请日：1990-09-28
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C7/00
CPC分类号： G11C7/1075 , G11C7/1015
摘要： A function selection circuit includes a first signal generating circuit (2) for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit (5) for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.
摘要翻译：功能选择电路包括：第一信号发生电路（2），用于产生与多个输入信号状态的所有组合中的每一个相对应的多个第一信号; 和第二信号发生电路（5），用于选择多个第一信号的组合的多个逻辑和并产生对应于多个逻辑和中的每一个的第二信号，该第二信号选择性地激活由真值表指示的操作函数。

2. 发明公开

EP0359203A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0359203A2
公开(公告)日：1990-03-21
申请号：EP89116871.8
申请日：1989-09-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/409 , G11C11/408
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096
摘要： Memory cells (12,22...N2) disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by first gate means. One memory cell column in the n memory cell columns in a selected block is selected by second gate means. One memory cell (12,22...N2) in a selected memory cell column is selected by a row address. The data in a selected memory cell (12,22...N2) are stored in a register and output therefrom.
摘要翻译：设置在矩阵中的存储单元（12,22 ... N2）被分成多个块。每个块由n（n是大于2的正整数）的存储单元列构成。一个列由一个地址选择。所选块中n个存储单元列中的一个存储单元列由第一门装置选择。所选块中n个存储单元列中的一个存储单元列由第二门装置选择。所选存储单元列中的一个存储单元（12,22 ... N2）由行地址选择。所选存储单元（12,22 ... N2）中的数据被存储在寄存器中并由其输出。

3. 发明授权

EP0359203B1 Semiconductor memory device 失效
标题翻译：一种半导体存储器件。
公开(公告)号：EP0359203B1
公开(公告)日：1995-07-19
申请号：EP89116871.8
申请日：1989-09-12
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Toda, Haruki , Ohshima, Shigeo , Ikawa, Tatsuo
IPC分类号： G11C11/24 , G11C11/409 , G11C11/408
CPC分类号： G11C11/4097 , G11C11/408 , G11C11/4096

4. 发明公开

EP0459502A2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：EP0459502A2
公开(公告)日：1991-12-04
申请号：EP91108897.9
申请日：1991-05-31
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Tokonami, Katsuji , Ohshima, Shigeo
IPC分类号： H01L23/50 , H01L23/485
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014 , H01L2924/14 , H01L2224/45099 , H01L2224/05599
摘要： There is disclosed a semiconductor integrated circuit device having: external input signal leads (109A,B) provided outside a semiconductor chip (201); a power supply lead (108) provided outside the semiconductor chip (201); a first electrode (104A) connected to an internal circuit (102A) on the semiconductor chip (201), and arranged close to the external input signal lead (109A), wherein when the circuit (102A) is caused to be operative, the first electrode (104A) is connected to the external input signal lead (109A); and a second electrode (105A) connected to the first electrode (104A) on the semiconductor chip (201), and arranged close to said power supply lead (108), wherein when the circuit (102A) is not caused to be operative, the second electrode (105A) is connected to the power supply lead (108). This invention is also applicable to a device where there are provided a plurality of internal circuits (102a, 102b). In this case, a plurality of the first electrodes (104a, 104b) drawn out from the internal circuits (102A,102B) are arranged close to the external input signal lead (109A,109B), and a plurality of the second electrodes (105a, 105b) similarly drawn out from the internal circuits (102A,102B) are arranged close to the power supply lead (108).
摘要翻译：公开了一种半导体集成电路器件，其具有：设置在半导体芯片（201）外部的外部输入信号引线（109A，B）; 设置在半导体芯片（201）外部的电源引线（108）; 与半导体芯片（201）上的内部电路（102A）连接并靠近外部输入信号引线（109A）布置的第一电极（104A），其中当使电路（102A）工作时，第一电极电极（104A）连接到外部输入信号引线（109A）; 以及与所述半导体芯片（201）上的所述第一电极（104A）连接并靠近所述电源引线（108）设置的第二电极（105A），其中，当所述电路（102A）未被致动时，所述第二电极（105A）连接到电源引线（108）。本发明也适用于提供多个内部电路（102a，102b）的设备。在这种情况下，从内部电路（102A，102B）引出的多个第一电极（104a，104b）被布置为靠近外部输入信号引线（109A，109B），并且多个第二电极，105b）从内部电路（102A，102B）类似地引出靠近电源引线（108）布置。

5. 发明授权

EP0432509B1 Semiconductor memory device 失效
公开(公告)号：EP0432509B1
公开(公告)日：1997-06-11
申请号：EP90121917.0
申请日：1990-11-15
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kiryu, Masakazu , Ohshima, Shigeo
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/00 , G11C11/4096

6. 发明公开

EP0496391A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0496391A2
公开(公告)日：1992-07-29
申请号：EP92101072.4
申请日：1992-01-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ikawa, Tatsuo, 201, Mason Ishizuka , Ohshima, Shigeo
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G11C7/1075 , G11C29/02
摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell (1) array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array (1); a mode switching unit (203) for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit (104, 201, 501) for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit (203).
摘要翻译：一种半导体存储器件，具有：用于随机存取具有以矩阵形式布置的存储单元的存储单元（1）阵列的RAM端口; 用于串行访问存储单元阵列（1）的一行的数据的SAM端口; 模式切换单元，用于在外部接收模式切换信号时，将SAM端口的操作模式切换到普通数据输出模式和测试模式之间; 以及地址指针输出单元（104,201,501），用于当通过模式切换单元（203）将操作模式切换到测试模式时，输出SAM端口的地址指针。

7. 发明授权

EP0459502B1 Semiconductor integrated circuit device 失效
标题翻译： Integrierte Halbleiterschaltungsanordung
公开(公告)号：EP0459502B1
公开(公告)日：1997-01-08
申请号：EP91108897.9
申请日：1991-05-31
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Tokonami, Katsuji , Ohshima, Shigeo
IPC分类号： H01L23/50 , H01L23/485
CPC分类号： H01L24/06 , H01L23/5286 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/48227 , H01L2224/49113 , H01L2924/00014 , H01L2924/14 , H01L2224/45099 , H01L2224/05599

8. 发明公开

EP0496391A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0496391A3
公开(公告)日：1993-09-29
申请号：EP92101072.4
申请日：1992-01-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ikawa, Tatsuo, 201, Mason Ishizuka , Ohshima, Shigeo
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G11C7/1075 , G11C29/02
摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell (1) array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array (1); a mode switching unit (203) for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit (104, 201, 501) for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit (203).

9. 发明公开

EP0432509A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeicheranordnung。
公开(公告)号：EP0432509A2
公开(公告)日：1991-06-19
申请号：EP90121917.0
申请日：1990-11-15
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Kiryu, Masakazu , Ohshima, Shigeo
IPC分类号： G11C7/00 , G11C11/409
CPC分类号： G11C7/00 , G11C11/4096
摘要： A semiconductor memory device comprises a memory cell array, a row decoder (RD), a column decoder (CP1), registers (CR) and a control unit (BLW). The control unit (BLW) allows the write operational mode of the column decoder (CD1) to switch. In the ordinary write operational mode, data in the n registers (CR) are written into the active memory cells of the n memory cell columns in one column block (CB) selected by the column decoder, respectively. In the block write mode, data in the n registers are written into active memory cells of the n memory cell columns in the 2 N column blocks selected by the column decoder, respectively.
Another semiconductor memory device comprises N memory units (UNT). Each memory unit (UNT) comprises a memory cell array, a row decoder (RD), a first column decoder (CP1), a second column decoder (CD2), a data input terminal (WI/O), registers (CR) and a control circuit. The control circuit is operative to allow the operational mode. When the device is in the ordinary mode, data latched in the register (CR) is written into one memory cell (MC) connected to one word line (WL) selected by the row decoder (RD) of one column selected by the first column decoder (CD1) of column blocks (CB) selected by the second decoder (CD2). While when the device is in the block write mode, data latched in the register (CR) is written at the same time into j memory cells (MC) connected to one word line (WL) selected by the row decoder (RD) of column blocks (CB) selected by the second column decoder (CD2).
摘要翻译：半导体存储器件包括存储单元阵列，行解码器（RD），列解码器（CP1），寄存器（CR）和控制单元（BLW）。控制单元（BLW）允许列解码器（CD1）的写操作模式切换。在普通写操作模式中，n个寄存器（CR）中的数据分别被写入由列解码器选择的一个列块（CB）中的n个存储单元列的有效存储单元中。在块写入模式中，n个寄存器中的数据分别被写入由列解码器选择的2 列中的n个存储单元列的有效存储单元。另一半导体存储器件包括N个存储单元（UNT）。每个存储器单元（UNT）包括存储单元阵列，行解码器（RD），第一列解码器（CP1），第二列解码器（CD2），数据输入端（WI / O），寄存器（CR）和一个控制电路。控制电路可操作以允许操作模式。当设备处于普通模式时，锁存在寄存器（CR）中的数据被写入连接到由第一列选择的一列的行解码器（RD）选择的一个字线（WL）的一个存储单元（MC）由第二解码器（CD2）选择的列块（CB）的解码器（CD1）。当器件处于写入模式时，寄存器（CR）中锁存的数据被同时写入连接到由行解码器（RD）的列选择的一个字线（WL）的j个存储器单元（MC）块（CB）由第二列解码器（CD2）选择。

10. 发明授权

EP0496391B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0496391B1
公开(公告)日：1997-06-11
申请号：EP92101072.4
申请日：1992-01-23
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA MICRO-ELECTRONICS CORPORATION
发明人： Ikawa, Tatsuo, 201, Mason Ishizuka , Ohshima, Shigeo
IPC分类号： G11C7/00
CPC分类号： G11C29/20 , G11C7/1075 , G11C29/02
摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell (1) array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array (1); a mode switching unit (203) for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit (104, 201, 501) for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit (203).
摘要翻译：一种半导体存储器件，具有：RAM端口，用于随机访问具有以矩阵设置的存储单元的存储单元（1）阵列; SAM端口，用于串行访问存储器单元阵列（1）的一行的数据; 模式切换单元（203），用于在从外部接收模式切换信号时，将所述SAM端口的操作模式在普通数据输出模式和测试模式之间切换; 以及地址指针输出单元（104,201,501），用于当模式切换单元（203）将操作模式切换到测试模式时输出SAM端口的地址指针。

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