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1. 发明公开

EP2901484A1 SELF-ALIGNED STRUCTURES AND METHODS FOR ASYMMETRIC GAN TRANSISTORS&ENHANCEMENT MODE OPERATION 审中-公开
标题翻译：自对准结构和方法，增益模式不对称的晶体管和GAN-OPERATION
公开(公告)号：EP2901484A1
公开(公告)日：2015-08-05
申请号：EP13841467.7
申请日：2013-06-12
申请人： Intel Corporation
发明人： DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , MUKHERJEE, Niloy , GOEL, Niti , KABEHIE, Sanaz , SUNG, Seung Hoon , PILLARISETTY, Ravi , CHAU, Robert S.
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7784 , H01L21/0254 , H01L21/2233 , H01L21/2236 , H01L21/2654 , H01L21/26546 , H01L21/31111 , H01L21/31144 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/207 , H01L29/42376 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.
摘要翻译：实施例包括高电子迁移率晶体管（HEMT）。在实施例中，栅电极被从源间隔开不同的距离和漏半导体区域，以提供高击穿电压和低导通状态电阻。在实施例中，自对准技术应用于以形成沟槽和到中间芯棒unabhängig限定与单个掩蔽操作的栅极长度，栅极 - 源极长度，栅极 - 漏极长度的电介质衬垫。在实施方案中，III-N HEMT器件包括用于阈值电压调节和/或增强模式操作氟掺杂的半导体势垒层。

2. 发明公开

EP3161866A1 DECOUPLING CAPACITORS AND ARRANGEMENTS 有权
标题翻译：解耦电容和安排
公开(公告)号：EP3161866A1
公开(公告)日：2017-05-03
申请号：EP14895959.6
申请日：2014-06-27
申请人： Intel Corporation
发明人： BOU-GHAZALE, Silvio E. , ELSAYED, Rany T. , GOEL, Niti
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L23/5223 , H01L27/0629 , H01L27/0733 , H01L28/88 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly may include a base layer in which a transistor is disposed, a first metal layer, and a second metal layer disposed between the base layer and the first metal layer. The transistor assembly may also include a capacitor, including a sheet of conductive material with a channel therein, disposed in the base layer or the second metal layer and coupled to a supply line of the transistor. Other embodiments may be disclosed and/or claimed.
摘要翻译：本文公开了晶体管组件，集成电路器件和相关方法的各种实施例。在一些实施例中，晶体管组件可以包括其中设置晶体管的基极层，第一金属层以及设置在基极层和第一金属层之间的第二金属层。所述晶体管组件还可以包括电容器，所述电容器包括其中具有沟道的导电材料片，所述电容器设置在所述基极层或所述第二金属层中并且耦合到所述晶体管的供应线。其他实施例可以被公开和/或要求保护。

3. 发明公开

EP3050111A1 IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON 审中-公开
标题翻译： VERBESSERTE MANTELSCHICHT-EPITAXIE DURCH SCHABLONENBEARBEITUNGFÜR异味整合AUF SILIIUM
公开(公告)号：EP3050111A1
公开(公告)日：2016-08-03
申请号：EP13894331.1
申请日：2013-09-27
申请人： Intel Corporation
发明人： MUKHERJEE, Niloy , RADOSAVLJEVIC, Marko , KAVALIEROS, Jack T. , PILLARISETTY, Ravi , GOEL, Niti , LE, Van H. , DEWEY, Gilbert , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7853 , H01L21/02381 , H01L21/02428 , H01L21/02538 , H01L29/0673 , H01L29/0688 , H01L29/42392 , H01L29/66431 , H01L29/66462 , H01L29/66795 , H01L29/78696
摘要： An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.
摘要翻译：一种包括半导体本体的装置，包括沟道区和设置在沟道区的相对侧上的结区，所述半导体本体包括包括第一带隙的第一材料; 以及包括第二材料的多个纳米线，所述第二材料包括不同于所述第一带隙的第二带隙，所述多个纳米线设置在穿过所述第一材料的分开的平面中，使得所述第一材料围绕所述多个纳米线中的每一个; 以及设置在通道区域上的栅极堆叠。一种方法，包括在衬底上方的分离平面中形成多个纳米线，所述多个纳米线中的每一个包括包括第一带隙的材料; 在所述多个纳米线中的每一个周围分别形成包层材料，所述包层材料包括第二带隙; 聚结包层材料; 以及在所述包层材料上设置栅极堆叠。

4. 发明公开

EP3050091A1 GE AND III-V CHANNEL SEMICONDUCTOR DEVICES HAVING MAXIMIZED COMPLIANCE AND FREE SURFACE RELAXATION 审中-公开
标题翻译：锗和III-V族沟道半导体装置和最大化的合规性，并且表面无松弛
公开(公告)号：EP3050091A1
公开(公告)日：2016-08-03
申请号：EP13894881.5
申请日：2013-09-27
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , DASGUPTA, Sansaptak , GOEL, Niti , LE, Van H. , RADOSAVLJEVIC, Marko , DEWEY, Gilbert , MUKHERJEE, Niloy , METZ, Matthew V. , RACHMADY, Willy , KAVALIEROS, Jack T. , CHU-KUNG, Benjamin , KENNEL, Harold W. , CEA, Stephen M. , CHAU, Robert S.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L27/0886 , H01L29/0653 , H01L29/1054 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/66545 , H01L29/66795 , H01L29/7842 , H01L29/7851
摘要： Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

5. 发明公开

EP2382667A2 TUNNEL FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME 有权
标题翻译：隧穿晶体管和场效应用于生产
公开(公告)号：EP2382667A2
公开(公告)日：2011-11-02
申请号：EP09836962.2
申请日：2009-12-17
申请人： Intel Corporation
发明人： GOEL, Niti , TSAI, Wilman , KAVALIEROS, Jack
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/205 , H01L29/66356
摘要： A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate region (140, 240) adjacent to the channel region. The source region contains a first compound semiconductor including a first Group III material and a first Group V material, and the channel region contains a second compound semiconductor including a second Group III material and a second Group V material. The drain region may contain a third compound semiconductor including a third Group III material and a third Group V material.

7. 发明公开

EP3167452A1 TECHNIQUES TO ACHIEVE AREA REDUCTION THROUGH CO-OPTIMIZING LOGIC CORE BLOCKS AND MEMORY REDUNDANCIES 审中-公开
标题翻译：技术，以减少区域通过协同优化逻辑核心模块和内存冗余
公开(公告)号：EP3167452A1
公开(公告)日：2017-05-17
申请号：EP14897113.8
申请日：2014-07-08
申请人： Intel Corporation
发明人： BOU-GHAZALE, Silvio E. , GHOSH, Abhik , GOEL, Niti
IPC分类号： G11C29/00 , G11C5/02
CPC分类号： G03F7/705 , G06F11/2041 , G06F17/5068 , G06F17/5081 , G11C5/025 , G11C29/702 , G11C29/814 , G11C29/816 , G11C29/88
摘要： Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.
摘要翻译：技术是游离缺失盘用于通过确定性采矿实现减少嵌入式存储器阵列的尺寸的备用芯布局。输入参数包括全球过程参数与设计特性相结合，以计算产率值对应于一个，实施例中的潜在冗余配置。所得的产率可以与确定性矿哪个冗余配置是合适的，以保持特定的产率。 A中的配置有一个或多个备用芯（无冗余存储器文献）导致的产率的所有其等同于或超过一个的与常规的存储器冗余的产率。在一些示例性情况下，存储器的冗余从芯消除。另一实施例提供具有包含在冗余芯阵列的半导体结构，每一个都包括存储器阵列和逻辑结构，每个冗余芯的存储器阵列的worin至少一种的组合物实现，而不行冗余和列冗余中的至少一个。

8. 发明公开

EP2901472A1 TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S) 有权转让
标题翻译：抓斗LIMITED外延BRED元件层（DE）
公开(公告)号：EP2901472A1
公开(公告)日：2015-08-05
申请号：EP13840768.9
申请日：2013-06-20
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , SUNG, Seung Hoon , GOEL, Niti , KAVALIEROS, Jack T. , DASGUPTA, Sansaptak , LE, Van H. , RACHMADY, Willy , RADOSAVLJEVIC, Marko , DEWEY, Gilbert , THEN, Han Wui , MUKHERJEE, Niloy , METZ, Matthew V. , CHAU, Robert S.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/20
CPC分类号： H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

9. 发明公开

EP3161854A1 TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS 审中-公开
标题翻译：法制造密度泛函单元的排列
公开(公告)号：EP3161854A1
公开(公告)日：2017-05-03
申请号：EP14896073.5
申请日：2014-06-25
申请人： Intel Corporation
发明人： ELSAYED, Rany, T. , GOEL, Niti , BOU-GHAZALE, Silvio, E. , ASKSAMIT, Randy, J.
IPC分类号： H01L21/027 , H01L21/768
CPC分类号： H01L27/0207 , G06F17/5068 , H01L21/0274 , H01L21/0277 , H01L21/823475 , H01L27/11 , H01L27/11807 , H01L29/16 , H01L2027/11853 , H01L2027/11866 , H01L2027/11875 , H03K19/00
摘要： Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.
摘要翻译：技术是圆盘游离缺失用于形成使用下一代光刻（NGL）的过程，：例如电子束直写（EBDW）和极紫外光刻（EUVL），以形成所述阵列中的单元的边界功能性细胞的压实的阵列。细胞的压实的阵列可用于现场可编程门阵列（FPGA）与逻辑单元配置的结构，静态随机存取存储器（SRAM）与位单元，或其它存储器或具有基于细胞的结构逻辑器件配置结构。的技术可以用来获得在10面积％至50％的降低，例如，对于功能单元的阵列，因为NGL工艺允许更高的精度和对小区边界更靠近切割，相比于传统的193nm光刻，此外，使用NGL工艺，以形成用于细胞因此可以减少光刻引起的变化，否则也将存在与常规的193nm的光刻法的边界。

10. 发明公开

EP2901490A1 SEMICONDUCTOR DEVICE HAVING GERMANIUM ACTIVE LAYER WITH UNDERLYING PARASITIC LEAKAGE BARRIER LAYER 有权
标题翻译：与锗活动层半导体部件包括架空寄生泄漏阻隔件
公开(公告)号：EP2901490A1
公开(公告)日：2015-08-05
申请号：EP13842724.0
申请日：2013-06-24
申请人： Intel Corporation
发明人： PILLARISETTY, Ravi , GOEL, Niti , THEN, Han Wui , LE, Van H. , RACHMADY, Willy , RADOSAVLJEVIC, Marko , DEWEY, Gilbert , CHU-KUNG, Benjamin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/28255 , H01L29/0673 , H01L29/1054 , H01L29/1079 , H01L29/1083 , H01L29/16 , H01L29/42392 , H01L29/66439 , H01L29/785 , H01L29/78696
摘要： Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

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