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1. 发明授权

EP1068570B1 PROCESSOR HAVING MULTIPLE PROGRAM COUNTERS AND TRACE BUFFERS OUTSIDE AN EXECUTION PIPELINE 有权
标题翻译：与多个程序米，跟踪缓冲器OUTSIDE执行流水线处理器
公开(公告)号：EP1068570B1
公开(公告)日：2005-04-06
申请号：EP98963903.4
申请日：1998-12-11
申请人： INTEL CORPORATION
发明人： AKKARY, Haitham , CHOW, Kingsum
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/3834 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3863
摘要： In one embodiment of the invention, a processor (50) includes an execution pipeline (108) to concurrently execute at least portions of threads T1-T4, wherein at least one of the threads is dependant on at least another one of the threads. The processor (50) also includes detection circuitry to detect speculation errors in the execution of the threads T1-T4. In another embodiment, the processor (50) includes thread management logic (124) to control dynamic creation of threads from a program (112A).

2. 发明公开

EP3022657A1 TECHNIQUES FOR CONTROLLING USE OF LOCKS 审中-公开
标题翻译： TECHNIKEN ZUR STEUERUNG DER VERWENDUNG VONSCHLÖSSERN
公开(公告)号：EP3022657A1
公开(公告)日：2016-05-25
申请号：EP13889446.4
申请日：2013-07-15
申请人： Intel Corporation
发明人： BAN, Khun , CHOW, Kingsum , AUNDHE, Shirish , VISWANATHAN, Sandhya
IPC分类号： G06F15/16
CPC分类号： G06F9/52 , G06F8/70 , G06F9/30076 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/528
摘要： Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.
摘要翻译：各种实施例通常涉及用于控制通过同时执行的代码部分来调节对共享资源的访问的锁的使用的技术。用于控制资源锁定的装置包括处理器组件，历史分析器，用于由处理器组件执行以用锁定标记来分析代替第一代码代码的锁定指令的至少一个结果，以允许处理器组件推测性地执行代码的第二实例，以及用于由处理器组件执行的锁定组件，以基于至少一个结果的分析，用于访问资源的代码的第一和第二实例来代替具有锁定标记的锁定指令;以及锁定指令，请求对该资源的访问锁定到第一个代码。描述和要求保护其他实施例。

3. 发明公开

EP3049962A1 MECHANISM FOR FACILITATING DYNAMIC AND PROACTIVE DATA MANAGEMENT FOR COMPUTING DEVICES 有权
标题翻译：机制，动态和前瞻性的数据管理，计算机设备PERMIT
公开(公告)号：EP3049962A1
公开(公告)日：2016-08-03
申请号：EP13894295.8
申请日：2013-09-27
申请人： Intel Corporation
发明人： HUANG, Yicong , CHOW, Kingsum
IPC分类号： G06F17/30
CPC分类号： G06F17/30306 , G06F7/02 , G06F11/3037 , G06F11/3433 , G06F17/3007 , G06F17/30132 , G06F17/30221 , G06F17/3053 , G06F17/30598 , G06F17/30864 , G06F17/30943
摘要： A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described herein, includes tracking one or more factors relating to a plurality of data sets, evaluating the plurality of data sets based on the one or more factors. The evaluating may include speculating at least one of relevancy and accessibility of each of the plurality of data sets. The method may further include generating data scores, the data scores being associated with the plurality of data sets based on the evaluation of the plurality of data sets, performing a first comparison of the data scores of the plurality of data sets with a criteria score, and classifying each data set based on the first comparison. The classifying may include setting caching order for each data set of the plurality of data sets.
摘要翻译：一种机制描述了一种用于促进动态数据管理用于计算设备的gemäß一个实施例。实施例的方法中，如所描述的，包括跟踪与数据集的多个一种或多种因素的影响，评估基于所述一个或多个因素的数据集的多元性。该评估可以包括推测每个数据集的所述多个的相关性和可访问性中的至少一个。该方法可以进一步包括生成数据的分数，所述分数数据被基于数据集的所述多个评估数据集的所述多个相关联，在执行数据集的所述多个与标准评分的数据分数的第一比较，和分类基于所述第一比较每个数据集。所述分类可以包括设置为每个数据集的数据集的所述多个高速缓存顺序。

4. 发明公开

EP2972894A1 CACHE MANAGEMENT IN MANAGED RUNTIME ENVIRONMENTS FIELDS 审中-公开
标题翻译：高速缓存存储器管理在托管TERM环境领域
公开(公告)号：EP2972894A1
公开(公告)日：2016-01-20
申请号：EP14769048.1
申请日：2014-03-13
申请人： Intel Corporation
发明人： WU, Keqiang , CHOW, Kingsum , LEE, Yong-Fong
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0253 , G06F12/0815 , G06F12/0837
摘要： Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.

5. 发明公开

EP1068570A1 PROCESSOR HAVING MULTIPLE PROGRAM COUNTERS AND TRACE BUFFERS OUTSIDE AN EXECUTION PIPELINE 有权
标题翻译：与多个程序米，跟踪缓冲器OUTSIDE执行流水线处理器
公开(公告)号：EP1068570A1
公开(公告)日：2001-01-17
申请号：EP98963903.4
申请日：1998-12-11
申请人： INTEL CORPORATION
发明人： AKKARY, Haitham , CHOW, Kingsum
IPC分类号： G06F9/30 , G06F9/38 , G06F9/40
CPC分类号： G06F9/3842 , G06F9/3013 , G06F9/3834 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3863
摘要： In one embodiment of the invention, a processor (50) includes an execution pipeline (108) to concurrently execute at least portions of threads T1-T4, wherein at least one of the threads is dependant on at least another one of the threads. The processor (50) also includes detection circuitry to detect speculation errors in the execution of the threads T1-T4. In another embodiment, the processor (50) includes thread management logic (124) to control dynamic creation of threads from a program (112A).

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