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2. 发明公开

EP4443435A2 A VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES 审中-公开
公开(公告)号：EP4443435A2
公开(公告)日：2024-10-09
申请号：EP24190664.3
申请日：2020-05-26
申请人： Texas Instruments Incorporated
发明人： BHORIA, Naveen , ANDERSON, Timothy, David , HIPPLEHEUSER, Pete, Michael
IPC分类号： G11C29/52
CPC分类号： G06F13/1605 , G11C29/72 , G11C29/76 , G11C2029/040920130101 , G11C2029/041120130101 , G11C29/4401 , G11C29/52 , G06F12/0815 , G06F12/0897 , G06F2212/102120130101 , G06F11/1064 , Y02D10/00
摘要： An eviction method, comprising the steps of: detecting an idle activity on a processor interface; and in response to detecting the idle activity on the processor interface: determining a write-miss entry inside a victim cache; and draining the write-miss entry from the victim cache.

3. 发明授权

EP4170507B1 FLEXIBLE ON-DIE FABRIC INTERFACE 有权
公开(公告)号：EP4170507B1
公开(公告)日：2024-09-04
申请号：EP22209604.2
申请日：2020-09-15
IPC分类号： G06F13/42 , G06F12/0806
CPC分类号： G06F2213/002620130101 , G06F13/4295 , G06F12/0806 , G06F13/4265 , G06F12/0875 , G06F12/0815 , G06F12/1027 , G06F12/109

4. 发明授权

EP4208792B1 TRACKING REPEATED READS TO GUIDE DYNAMIC SELECTION OF CACHE COHERENCE PROTOCOLS IN PROCESSOR-BASED DEVICES 有权
公开(公告)号：EP4208792B1
公开(公告)日：2024-06-26
申请号：EP21733345.9
申请日：2021-05-28
IPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831

5. 发明公开

EP3311288A4 SHARED MEMORY CONTROLLER AND METHOD OF USING SAME 有权
公开(公告)号：EP3311288A4
公开(公告)日：2018-06-06
申请号：EP16823754
申请日：2016-06-14
申请人： HUAWEI TECH CO LTD
发明人： LUAN HAO , GATHERER ALAN , YANG BIN
IPC分类号： G06F13/16 , G06F12/0815
CPC分类号： G06F9/52 , G06F12/0815 , G06F13/1663
摘要： A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

6. 发明授权

EP1465059B1 Apparatus and method for renaming a cache line 有权转让
标题翻译：用于重命名缓存行的设备和方法
公开(公告)号：EP1465059B1
公开(公告)日：2018-05-09
申请号：EP03257877.5
申请日：2003-12-15
申请人： IP-First, LLC.
发明人： Hooker, Rodney
IPC分类号： G06F9/312
CPC分类号： G06F9/30032 , G06F9/3004 , G06F12/0815 , G06F12/0862 , G06F2212/6028
摘要： A microprocessor apparatus is provided that enables exclusive allocation and renaming a cache line. The apparatus includes translation logic and execution logic. The translation logic translates an allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first cache line in an exclusive state and to copy the contents of a second cache line into the first cache line. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first cache line in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second cache line into the first cache line.

7. 发明公开

EP3140749A4 IN-MEMORY LIGHTWEIGHT COHERENCY 有权
公开(公告)号：EP3140749A4
公开(公告)日：2018-01-10
申请号：EP15789090
申请日：2015-05-07
申请人： MICRON TECHNOLOGY INC
发明人： MURPHY RICHARD C
IPC分类号： G06F15/167 , G06F9/52 , G06F12/00 , G06F12/02 , G06F12/0815 , G06F12/0817 , G06F12/084 , G06F12/1072 , G11C5/02 , G11C8/12
CPC分类号： G11C8/12 , G06F9/52 , G06F12/0284 , G06F12/0815 , G06F12/0817 , G06F12/0824 , G06F12/084 , G06F12/1072 , G06F2212/1032 , G06F2212/1048 , G06F2212/251 , G06F2212/3042 , G11C5/02 , G11C5/025
摘要： A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

8. 发明公开

EP3126999A4 SESSION MANAGEMENT IN DISTRIBUTED STORAGE SYSTEMS 有权
公开(公告)号：EP3126999A4
公开(公告)日：2017-11-08
申请号：EP15772289
申请日：2015-03-31
申请人： AMAZON TECH INC
发明人： VINCENT PRADEEP
IPC分类号： G06F15/167 , G06F3/06 , G06F12/0815 , G06F17/30 , H04L29/06 , H04L29/08
CPC分类号： H04L67/1097 , G06F3/0622 , G06F3/0659 , G06F3/067 , G06F12/0815 , G06F17/30171 , H04L67/141 , H04L67/146 , H04L67/18 , H04L67/2842 , H04L69/28
摘要： A request for a session identifier for a particular client is transmitted from an access subsystem of a storage service to a metadata subsystem of the service. A session identifier based on a persistent session storage location at which metadata of the client session are stored is received at the access subsystem. The session identifier is cached at the access subsystem prior to its transmission to the client. A lock state indicator generated by the metadata subsystem in response to a particular request from the client during the client session may also be cached at the access subsystem. Subsequent storage requests from the client during the session may be handled by the access subsystem using the cached session identifier and lock state indicator.

9. 发明公开

EP3217616A1 MEMORY ACCESS METHOD, SWITCH AND MULTI-PROCESSOR SYSTEM 有权
标题翻译：存储器访问方法，开关和多处理器系统
公开(公告)号：EP3217616A1
公开(公告)日：2017-09-13
申请号：EP14907135.9
申请日：2014-11-28
申请人： Huawei Technologies Co., Ltd.
发明人： TAO, Yidong , HE, Rui , DONG, Xiaowen
IPC分类号： H04L12/911 , H04L29/12 , H04L12/721
CPC分类号： G06F12/0813 , G06F12/0815 , G06F13/1652 , G06F2211/005 , G06F2212/1024 , G06F2212/154 , H04L12/56 , H04L45/38 , H04L67/2842
摘要： Embodiments of the present invention provide a memory access method, a switch, and a multiprocessor system. The memory access method includes: receiving, by the switch, a data packet; matching a flow table on the data packet, where the flow table includes at least one flow entry, where the flow entry includes a matching field and an action field, and the at least one flow entry includes a first flow entry, where a matching field of the first flow entry is used to match source node information, destination node information, and a protocol type in the data packet, and an action field of the first flow entry is used to indicate an operation command for a storage device embedded in the switch; and when the data packet successfully matches the first flow entry, performing an operation on the storage device according to the operation command in the action field of the successfully matched first flow entry. In the present invention, a processor in a multiprocessor system accesses a storage device embedded in a switch, so as to reduce and even eliminate a possibility that the processor accesses a remote memory, and reduce a memory access delay.
摘要翻译：本发明的实施例提供了一种存储器访问方法，交换机和多处理器系统。该存储器访问方法包括：交换机接收数据包; 匹配所述数据报文的流表，所述流表中包括至少一个流表项，所述流表项包括匹配字段和动作字段，所述至少一个流表项包括第一流表项，其中匹配字段所述第一流表项的动作字段用于匹配所述数据包中的源节点信息，目的节点信息和协议类型，所述第一流表项的动作字段用于指示嵌入所述交换机中的存储设备的操作命令 ; 当数据包与第一流表项匹配成功时，根据匹配成功的第一流表项的动作域中的操作命令对存储设备进行操作。在本发明中，多处理器系统中的处理器访问嵌入在交换机中的存储设备，以减少甚至消除处理器访问远程存储器的可能性，并减少存储器访问延迟。

10. 发明公开

EP3206123A1 DATA CACHING METHOD AND DEVICE, AND STORAGE MEDIUM 有权
标题翻译：数据缓存方法和装置以及存储介质
公开(公告)号：EP3206123A1
公开(公告)日：2017-08-16
申请号：EP15850914.1
申请日：2015-04-28
申请人： Sanechips Technology Co., Ltd.
发明人： ZHAO, Jiao , LAI, Mingliang , TIAN, Haoxuan , CHANG, Yanrui
IPC分类号： G06F5/08
CPC分类号： H04L47/6245 , G06F12/0815 , G06F2212/1008 , G06F2212/154 , G06F2212/608 , H04L49/90
摘要： Disclosed is a data caching method, comprising: according to an input port number of a cell, storing the cell in a corresponding first-in first-out queue; determining that a cell to be dequeued can be dequeued in the current K th cycle, scheduling for the cell to be dequeued to be dequeued, acquiring the actual value of the number of splicing units occupied by the cell to be dequeued, and storing the cell to be dequeued in a register the same number of bits wide as a bus in a cell splicing manner, wherein determining that the cell to be dequeued can be dequeued is conducted in accordance with the fact that a first back pressure count value of the (K-1) th cycle is less than or equal to a first preset threshold value, and the first back pressure count value of the (K-1) th cycle is obtained in accordance with an estimated value of the number of the splicing units occupied when the previous cell to be dequeued is dequeued, the number of splicing units capable of being transmitted by the bus in each cycle, and a first back pressure count value of the (K-2) th cycle. Also disclosed at the same time are a data caching device and a storage medium.
摘要翻译：公开了一种数据缓存方法，包括：根据小区的输入端口号，将所述小区存储在对应的先入先出队列中; 确定出现的小区可以在当前的第K个周期出队，调度出队的出队出队，获取待出队的小区占用的拼接单元数的实际值，并将该小区存储到根据如下事实进行确定待出队的单元可以出队的步骤：在寄存器中以与单元接续方式的总线相同的比特数出队，其中，根据第（K- 1）周期小于或等于第一预设阈值，并且第（K-1）个循环的第一背压计数值根据当第（K-1）次循环时的拼接单元的数量的估计值来获得先前要出队的单元出队，在每个循环中能够由总线传送的拼接单元的数量以及第（K-2）个循环的第一背压计数值。同时还公开了一种数据缓存设备和一种存储介质。

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