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1. 发明公开

EP4379648A2 MACHINE LEARNING SPARSE COMPUTATION MECHANISM 审中-公开
公开(公告)号：EP4379648A2
公开(公告)日：2024-06-05
申请号：EP24171188.6
申请日：2018-03-08
申请人： INTEL Corporation
发明人： Nurvitadhi, Eriko , Vembu, Balaji , Lin, Tsung-Han , Sinha, Kamal , Barik, Rajkishore , Galoppo von Borries, Nicolas
IPC分类号： G06T1/20
CPC分类号： G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06F2212/102420130101 , G06F2212/30220130101 , G06F2212/62120130101 , G06F2212/40120130101 , G06T1/20 , G06N3/063 , G06N3/084 , Y02D10/00 , G06N3/044 , G06N3/045
摘要： A method and a data processing system for performing operations of a machine learning framework to facilitate a sparse matrix multiplication for convolutional layers are disclosed. Therefore, one or more primitives for enabling a compute kernel to specify one or more operations to be performed by the compute kernel of a graphics processor on an output of a sparse matrix multiplication operation are provided, the one or more operations including applying an activation function and the compute kernel being associated with the convolutional layers. An execution of the compute kernel to execute the sparse matrix multiplication operation on matrices relating to the convolutional layers and an execution of the compute kernel to apply the activation function to the output of the sparse matrix multiplication operation based on the one or more primitives are triggered.

3. 发明公开

EP4365727A1 SYSTEMS AND METHODS FOR COMPUTATIONAL ACCELERATION 审中-公开
公开(公告)号：EP4365727A1
公开(公告)日：2024-05-08
申请号：EP23202712.8
申请日：2023-10-10
申请人： Samsung Electronics Co., Ltd.
发明人： NGUYEN, Marie Mai , PITCHUMANI, Rekha , LI, Zongwang , KI, Yang Seok
IPC分类号： G06F3/06 , G06F13/16 , G06F13/28 , G06F12/0815
CPC分类号： G06F3/061 , G06F13/1668 , G06F12/0815
摘要： A system is described. The system may include a host processor, a host memory connected to the host processor, and a storage device connected to the host processor. An accelerator may communicate with the host processor. The accelerator may produce an output. The accelerator may also include a local memory, which may include a first region and a second region. The first region of the local memory of the accelerator may support a first mode, and the second region of the local memory of the accelerator may support a second mode. The accelerator may store the output of the accelerator in a destination, which may include the host memory, the storage device, the first region of the local memory of the accelerator, or the second region of the local memory of the accelerator.

4. 发明授权

EP4254202B1 CACHE COHERENCY PROTOCOL FOR ENCODING A CACHE LINE WITH A DOMAIN SHARED STATE 审中-实审
公开(公告)号：EP4254202B1
公开(公告)日：2024-04-24
申请号：EP23160989.2
申请日：2023-03-09
IPC分类号： G06F12/0815 , G06F12/0875
CPC分类号： G06F12/0815 , G06F12/0875

5. 发明公开

EP3404656A1 CONCEPT FOR BRIDGING THE GAP BETWEEN PARAMETRIC MULTI-CHANNEL AUDIO CODING AND MATRIXED-SURROUND MULTI-CHANNEL CODING 有权转让
公开(公告)号：EP3404656A1
公开(公告)日：2018-11-21
申请号：EP18180076.4
申请日：2006-06-21
申请人： FRAUNHOFER-GESELLSCHAFT zur Förderung der angewandten Forschung e.V. , Agere Systems, Inc.
发明人： Hilpert, Johannes , Faller, Christof , Linzmeier, Karsten , Sperschneider, Ralph
IPC分类号： G10L19/008 , G06F12/0815 , H04S3/02
CPC分类号： G06F12/0815 , G10L19/008 , H04S3/02
摘要： The purpose of the invention is to bridge the gap between parametric multi-channel audio coding and matrixed-surround multi-channel coding by gradually improving the sound of an up-mix signal while raising the bit-rate consumed by the side-information starting from 0 up to the bit-rates of the parametric methods. More specifically, it provides a method of flexibly choosing an "operating point" somewhere between matrixed-surround (no side-information, limited audio quality) and fully parametric reconstruction (full side-information rate required, good quality). This operating point can be chosen dynamically (i.e. varying over time) and in response to the permissible side-information rate, as it is dictated by the individual application.

6. 发明授权

EP2761464B1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 有权转让
公开(公告)号：EP2761464B1
公开(公告)日：2018-10-24
申请号：EP11873012.6
申请日：2011-09-30
申请人： Intel Corporation
发明人： RAMANUJAN, Raj, K. , AGARWAL, Rajat , HINTON, Glenn, J.
IPC分类号： G11C13/00 , G06F12/0893
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” In one embodiment, the “near memory” is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.

7. 发明公开

EP3385901A1 MACHINE LEARNING SPARSE COMPUTATION MECHANISM 审中-公开
公开(公告)号：EP3385901A1
公开(公告)日：2018-10-10
申请号：EP18160825.8
申请日：2018-03-08
申请人： INTEL Corporation
发明人： NURVITADHI, Eriko , VEMBU, Balaji , LIN, Tsung-Han , SINHA, Kamal , BARIK, Rajkishore , GALOPPO VON BORRIES, Nicolas C.
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/4881 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0888 , G06F17/16 , G06F2212/1024 , G06F2212/302 , G06F2212/621 , G06N3/04 , G06N3/08 , G06T1/60 , G06T15/005 , G06T2200/28
摘要： An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.

8. 发明公开

EP3385849A1 APPARATUS AND METHOD FOR PROTECTING CONTENT IN VIRTUALIZED AND GRAPHICS ENVIRONMENTS 审中-公开
公开(公告)号：EP3385849A1
公开(公告)日：2018-10-10
申请号：EP18159469.8
申请日：2018-03-01
申请人： INTEL Corporation
发明人： RAY, Joydeep , APPU, Abhishek R. , K, Pattabhiraman , VEMBU, Balaji , KOKER, Altug
IPC分类号： G06F12/0895 , G06F12/14
CPC分类号： G06F21/10 , G06F9/455 , G06F12/0815 , G06F12/0895 , G06F12/1425 , G06F2009/45587 , G06F2212/455 , G06T15/005 , H04L2209/603 , H04L2209/605 , H04N19/00 , H04N21/4405
摘要： An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

9. 发明公开

EP3380943A1 INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS 有权
公开(公告)号：EP3380943A1
公开(公告)日：2018-10-03
申请号：EP16869033.7
申请日：2016-09-28
申请人： Intel Corporation
发明人： SASANKA, Ruchira
IPC分类号： G06F12/0811
CPC分类号： G06F12/0875 , G06F9/30047 , G06F9/383 , G06F12/0811 , G06F12/0815 , G06F12/0817 , G06F12/0888 , G06F12/0895 , G06F12/1045 , G06F2212/1021 , G06F2212/621
摘要： In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

10. 发明公开

EP3355525A4 COMPUTING APPARATUS, NODE DEVICE, AND SERVER 有权转让
公开(公告)号：EP3355525A4
公开(公告)日：2018-08-01
申请号：EP16854829
申请日：2016-08-16
申请人： HUAWEI TECH CO LTD
发明人： XU JIANRONG , ZHENG WEI
IPC分类号： H04L12/46 , G06F12/0815
CPC分类号： H04L12/46 , G06F12/0815
摘要： The present invention discloses a computing apparatus, including: at least one general computing core circuit, an internal interface circuit, an external interface circuit, a cache coherence engine circuit, and a protocol conversion circuit. The computing apparatus is coupled to an internal apparatus by using the internal interface circuit, and is coupled to an external apparatus by using the external interface circuit. When working in a first mode, the cache coherence engine circuit implements cache coherence between the computing apparatus, the internal apparatus, and the external apparatus, and in this case, the computing apparatus is used as a node controller. When working in a second mode, the cache coherence engine circuit processes only cache coherence between the apparatus and the internal apparatus, and the external interface circuit is used as a network interface circuit. The present invention further discloses a node device and a server. By means of the foregoing manner, in the present invention, different working modes of the computing apparatus can be configured, so that different types of servers may be constituted by using apparatuses of a same type, thereby implementing flexible switching between different solutions.

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